MU9C3480L-12DC データシートの表示（PDF） - Music Semiconductors

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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

OPERATIONAL CHARACTERISTICS

Throughout the following, “aaaH” represents a

three-digit hexadecimal number “aaa,” while “bbB”

represents a two-digit binary number “bb.” All memory

locations are broken into 16-bit segments. Segment 0

corresponds with the lowest order bits (bits 15-0) while

the higher segments, labeled 1, 2, and 3, contain bits

31-16, 47-32 and 63-48, respectively.

THE CONTROL BUS

Refer to the Block Diagram for the following discussion.

The primary control mechanism for the MU9C3480L are

the input signals Chip Enable (/E), Write Enable (/W),

Command Enable (/CM), and Enable Daisy Chain (/EC).

The /EC input of the Control bus is responsible for

enabling the /MF Match flag output when LOW, and

controlling the daisy-chain operation. The secondary

control mechanism of the MU9C3480L is by instructions

which are decoded by the Instruction decoder. Logical

combinations of the Control Bus inputs, coupled with the

execution of Select Persistent Source (SPS), Select

Persistent Destination (SPD), and Temporary Command

Override (TCO) instructions, allow the I/O operations to

and from the DQ15-DQ0 lines to the internal resources,

as shown in Table 3.

The default source and destination for Data Read and

Write cycles is the Comparand register. This default

state can be overridden independently by executing a

Select Persistent Source or Select Persistent

Destination instruction, selecting a different source or

destination for data. Subsequent Data Read or Data

Write cycles will access that source or destination until

another SPS or SPD instruction is executed. The

currently selected persistent source or destination can

be read back via a TCO PS or PD instruction. The

sources and destinations available for persistent access

are those resources on the 64-bit bus: Comparand

register, Mask Register 1, Mask Register 2, and the

Memory array.

The default destination for Command Write cycles is the

Instruction decoder, while the default source for

Command Read cycles is the Status register.

Access to the Control register, the Page Address

register, the Segment Control register, the Address

register, the Next Free Address register, and Device

Select register is by Temporary Command Override

(TCO) instructions which are only active for one

Command Read or Write cycle after being loaded into

the Instruction decoder.

The data and control interfaces to the MU9C3480L are

synchronous. During a Write cycle, the Control and Data

inputs are registered by the falling edge of /E. When

writing to the persistently selected data destination, the

Destination Segment counter is clocked by the rising

edge of /E. During a Read cycle, the Control inputs are

registered by the falling edge of /E, and the Data outputs

are enabled while /E is LOW. When reading from the

persistently selected data source, the Source Segment

counter is clocked by the rising edge of /E.

THE REGISTER SET

The Control, Segment Control, Address, Mask Register

1, and the Persistent Source and Destination registers

are duplicated, with one set termed the Foreground set,

and the other the Background set. The active set is

chosen by issuing Set Foreground Active or Set

Background Active instructions. By default, the

Foreground set is active after a Reset. Having two

alternate sets of registers that determine the device

configuration allows for a rapid return to a foreground

network filtering task from a background housekeeping

task.

Writing a value to the Control register or writing data to

the last segment of the Comparand or either Mask

register will cause an automatic comparison to occur

between the contents of the Comparand register and the

words in the CAM segments of the memory marked

valid, masked by MR1 or MR2 if selected in the Control

register.

Instruction Decoder

The Instruction decoder is the write-only decode logic for

instructions and is the default destination for Command

Write cycles. The lower-order 12 bits comprise the

instruction, as shown in the Instruction Set Description.

Bit 11 is a flag that notifies the LANCAM that the

instruction is a two-cycle instruction and requires an

absolute address to be loaded into the Address register

on the next cycle. If the Address flag is not set, the

memory access occurs at the address currently

contained in the Address register.

Control Register (CT)

The Control register is composed of a number of

switches that configure the LANCAM, as shown in Table

4, and is written to or read from using a TCO CT

instruction. If bit 15 of the value written following the TCO

CT is a “0”, the device is Reset (and all other bits are

ignored.) See Table 5 for the reset state. A write to the

Control register causes an automatic compare to occur

(except in case of a Reset.) Either the Foreground or

Background Control register will be active, depending on

which has been selected, and only the active Control

register will be written to or read.

If the Match Flag is disabled via bits 14 and 13, the

internal match condition, /MA(int), used to determine a

daisy-chained device’s response, is forced HIGH as

shown in Tables 8a and 8b, so that Case 6 is not

possible, effectively removing the device from the

Rev. 1.0 Draft Web

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