MU9C3480L-12DC データシートの表示（PDF） - Music Semiconductors
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MU9C3480L-12DC Datasheet PDF : 24 Pages
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MU9C3480L
LANCAM®
OPERATIONAL CHARACTERISTICS (CONT’D)
15 14 13 12 11
RST Match Flag Full Flag
R
Enable
Enable
E
= “00”
= “00”
S
Disable
Disable
E
= “01”
= “01”
T No Change No Change
=
= “11”
= “11”
“0”
10 9
Translation
Input Not
Translated
= “00”
Input
Translated
= “01"
No Change
= “11"
8
7
6
5
4
3
2
1
0
CAM/RAM Part. Comp. Mask AR Inc/Dec Mode
64 CAM/0 RAM = “000”
48 CAM/16 RAM = “001”
32 CAM/32 RAM = “010”
16 CAM/48 RAM = “011”
48 RAM/16 CAM = “100”
32 RAM/32 CAM = “101”
16 RAM/48 CAM = “110”
No Change = “111”
None = “00”
MR1 = “01”
MR2 = “10”
No Change
= “11”
Increment
= “00”
Decrement
= “01”
Disable
= “10”
No Change
= “11”
1480 Mode
= “00”
2480 Mode
= “01”
Reserved
= “10”
No Change
= “11”
Table 4: Control Register Bit Assignments
CAM Status
Validity bits at all memory locations
Match and Full Flag outputs
IEEE 802.3-802.5 Input Translation
CAM/RAM Partitioning
Comparison Masking
Address register auto-increment or -decrement
Source and Destination Segment Counters Count Ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (Including CT15)
Persistent Destination for Command Writes
Persistent Source for Command Reads
Persistent Source and Destination for Data Reads and Writes
Operating Mode
Configuration Register Set
After /RESET is asserted
Skip = 0, Empty = 1
Enabled
Not Translated
64 bits CAM, 0 bits RAM
Disabled
Disabled
00B to 11B; loaded with 00B
Contains all "0"s
Contain all “0”s
Contains 0008H
Instruction decoder
Status register
Comparand register
1480
Foreground
Software Reset
Same
Same
Same
Same
Same
Same
Same
Same
Unchanged
Same
Same
Same
Same
Same
Same
Table 5: Device Control State after Reset
daisy-chain. With the Match Flag disabled, /MF=/MI,
and operations directed to Highest-priority Match
locations are ignored. Normal operation of the device is
with the /MF enabled. The Match Flag Enable field has
no effect on the /MA or /MM bits in the Status register.
These bits always reflect the true state of the device.
enabled, the bits are reordered as shown in Figure 7.
The CAM/RAM partitioning is controlled at bits 8-6, and
may be set in 16-bit increments. The CAM portion of
each word may be sized from a full 64 bits down to 0
bits. The RAM portion can be at either end of the 64-bit
word.
If the Full Flag is disabled via bits 12 and 11, the device
behaves as if it is full and ignores instructions to Next
Free Address. Additionally, writes to the Page Address
register will be disabled. All other instructions operate
normally. Additionally, with the /FF disabled, /FF=/FI.
Normal operation of the device is with the /FF enabled.
The Full Flag Enable field has no effect on the /FL
Status register bit. This bit always reflects the true state
of the device.
The IEEE Translation control at bits 10 and 9 can be
used to enable the translation hardware for writes to
64-bit resources in the device. When translation is
Compare masks may be selected by bits 5 and 4. Mask
Register 1, Mask Register 2, or neither may be selected
to mask compare operations. The address register
behavior is controlled by bits 3 and 2, and may be set
to increment, decrement or neither after a memory
access. Bits 1 and 0 set the operating mode:
1480-compatible as shown in Table 8a, or
2480-compatible as shown in Table 8b. After a Reset,
the device comes up in the 1480 mode, following the
1480 operating responses in Table 8a. When switched
to the 2480 mode, a NOP is not required to unlock the
daisy chain after a non-matching compare, as in the
1480 mode.
Rev. 1.0 Draft Web
8
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