M5M5256DFP データシートの表示（PDF） - Renesas Electronics

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M5M5256DFP

262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

Renesas Electronics 

RENESAS LSIs

M5M5256DFP,VP-55LL,-70LL,-70LLI,

-55XL,-70XL

262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

FUNCTION

The operation mode of the M5M5256DFP,VP is

determined by a combination of the dev ice control inputs

/S, /W and /OE. Each mode is summarized in the f unction

table.

A write cy cle is executed whenev er the low lev el /W

ov erlaps with the low lev el /S. The address must be set

up bef ore the write cy cle and must be stable during the

entire cy cle. The data is latched into a cell on the trailing

edge of /W, /S, whichev er occurs f irst, requiring the set-

up and hold time relativ e to these edge to be maintained.

The output enable /OE directly controls the output stage.

Setting the /OE at a high lev el,the output stage is in a

high-impedance state, and the data bus contention

problem in the write cy cle is eliminated.

FUNCTION TABLE

A read cy cle is executed by setting /W at a high lev el

and /OE at a low lev el while /S are in an activ e state.

When setting /S at a high lev el, the chip is in a non-

selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a high-

impedance state, allowing OR-tie with other chips and

memory expansion by /S. The power supply current is

reduced as low as the stand-by current which is specif ied

as Icc3 or Icc4, and the memory data can be held at

+2V power supply , enabling battery back-up operation

during power f ailure or power-down operation in the non-

selected mode.

/S /W /OE

Mode

DQ

Icc

H X X Non selection High-impedance

Stand-by

L LX

Write

DIN

Activ e

L HL

Read

D OUT

Activ e

L HH

High-impedance

Activ e

Note • "H" and "L" in this table mean VIH and VIL, respectiv ely .

• "X" in this table should be "H" or "L".

BLOCK DIAGRAM

ADDRESS

INPUT

A 8 25

A 13 26

A 14 1

A 12 22

A7 3

A6 4

A5 5

A4 6

A3 7

A2 8

A1 9

A 0 10

A 10 21

A 11 23

A 9 24

WRITE CONTROL

INPUT /W 27

CHIP SELECT

INPUT /S

20

OUTPUT ENABLE /OE 22

INPUT

32768 WORD

X 8BIT

(512 ROWS X

512 COLUMNS)

CLOCK

GENERATOR

11 DQ1

12 DQ2

13 DQ3

15 DQ4

16 DQ5

17 DQ6

18 DQ7

19 DQ8

DATA I/O

28 VCC

(5V)

14 GND

(0V)

2

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