LTC6903HMS8-TRPBF データシートの表示（PDF） - Linear Technology
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LTC6903HMS8-TRPBF Datasheet PDF : 14 Pages
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LTC6903/LTC6904
APPLICATIONS INFORMATION
Output Control
The CLK and CLK outputs of the LTC6903/LTC6904 are
individually controllable through the serial port as de-
scribed in Table 2 below. The low power mode may also
be accessed through these control bits. It is preferred
that unused outputs be disabled in order to reduce power
dissipation and improve accuracy.
Disabling an unused output will improve accuracy of
operation at frequencies above 1MHz. An unused output
running with no load typically degrades frequency ac-
curacy up to 0.2% at 68MHz. An unused output running
into a 5pF load typically degrades frequency accuracy up
to 0.5% at 68MHz.
Table 2. Output Configuration
CNF1
CNF0
CLK
CLK
0
0
ON
CLK + 180°
0
1
OFF
ON
1
0
ON
OFF
1
1
Powered-Down*
*Powered-Down: When in this mode, the chip is in a low power state
and will require approximately 100µs to recover. This is not the same
effect as the OE pin, which is fast, but uses more power supply current.
Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15
OCT3
D7
DAC5
D14
OCT2
D6
DAC4
D13
OCT1
D5
DAC3
D12
OCT0
D4
DAC2
D11
DAC9
D3
DAC1
D10
DAC8
D2
DAC0
D9
DAC7
D1
CNF1
D8
DAC6
D0
CNF0
Serial Port Register Description
OCT[3:0] – Frequency Divider Setting. (See Frequency
Setting Information Section)
DAC[9:0] – Master Oscillator Frequency Setting. (See
Frequency Setting Information Section)
CNF[1:0] – Output Configuration. This controls outputs
CLK and CLK according to Table 2.
LTC6903 SPI Compatible Interface
A serial data transfer is composed of sixteen (16) bits of
data labeled D15 through D0. D15 is the first bit of data
presented in each transaction. All serial port register bits
are set LOW on power-up.
Writing Data (LTC6903 Only)
When the SEN line is brought LOW, serial data presented
on the SDI input is clocked in on the rising edges of SCK
until SEN is brought HIGH. On every eighth rising edge
of SCK, the preceding 8-bits of data are clocked into the
internal register. It is therefore possible to clock in only
the 8 {D15 - D8} most significant bits of data rather than
completing an entire transfer.
The serial data transfer starts with the most significant
bit and ends with the least significant bit of the data, as
shown in the Timing Diagrams section.
69034fe
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