LTC6903HMS8-TRPBF データシートの表示（PDF） - Linear Technology
部品番号
コンポーネント説明
メーカー
LTC6903HMS8-TRPBF Datasheet PDF : 14 Pages
| |||
LTC6903/LTC6904
APPLICATIONS INFORMATION
LTC6904 I2C Interface
The LTC6904 communicates with a host (master) using the
standard I2C 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be HIGH when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required on
these lines. If the I2C interface is not driven with a standard
I2C compatible device, care must be taken to ensure that
the SDA line is released during the ACK cycle to prevent
bus contention.
The LTC6904 is a receive-only (slave) device. The master
can communicate with the LTC6904 using the write word
protocols as explained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
HIGH. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from LOW to HIGH while
SCL is HIGH. The bus is then free for communication with
another SMBus device.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The acknowledge related
clock pulse is generated by the master. The master releases
the SDA line (HIGH) during the acknowledge clock pulse.
The slave-receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains a stable LOW
during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC6904
with a START condition and a 7-bit address followed by
the write bit (Wr) = 0. The LTC6904 acknowledges and
the master delivers the most significant data byte. Again
the LTC6904 acknowledges and the data is latched into
the most significant data byte input register. The master
then delivers the least significant data byte. The LTC6904
acknowledges once more and latches the data into the
least significant data byte input register. Lastly, the master
terminates the communication with a STOP condition.
Slave Address
The LTC6904 can respond to one of two 7-bit addresses.
The first 6 bits (MSBs) have been factory programmed
to 001011. The address pin, ADR (Pin 4) is programmed
by the user and determines the LSB of the slave address,
as shown in the table below:
ADR (Pin 4)
0
1
LTC6904 Address
0010111
0010110
Write Word Protocol Used by the LTC6904
1
7
11
8
1
8
11
S Slave Address Wr A MS Data Byte A LS Data Byte A P
S = START Condition, Wr = Write Bit = 0, A = Acknowledge, P = STOP Condition
69034 F01
69034fe
11
Share Link: 