DSA400 データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

DSA400

Configurable Four Output, Low Jitter Clock Generator for Automotive

Microchip Technology 

DSA400

4.0 TERMINATION SCHEMES

4.1 LVPECL

VDD

130 Ω

100 Ω

130 Ω

82 Ω

82 Ω

FIGURE 4-1:

Typical LVPECL Termination Scheme.

TABLE 4-1: LVPECL OUTPUTS (Note 1)

Parameter Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

Peak-to-Peak

Output Swing

VOH VDD – 1.08 —

—

V Output Logic High, RL = 50Ω to VDD–2V

VOL

—

— VDD – 1.55

Output Logic Low, RL = 50Ω to VDD–2V

—

—

800

—

mV Single-Ended

Output

tR

Transition Time

(Note 2)

tF

—

250

—

—

250

—

Rise Time. 20% to 80%; RL = 50Ω to

ps VDD–2V

Fall Time. 20% to 80%; RL = 50Ω to VDD–

2V

Frequency

f0

2.3

—

460

MHz Single Frequency

Output Duty

Cycle

SYM

48

—

52

% Differential

IO Supply

Current (Note 3)

IDDIO

—

35

38

mA Per Output at 125 MHz

Period Jitter

(Note 4)

JPER

—

2.5

—

psRMS CLK(0:3) = 156.25 MHz

Integrated

Phase Noise

JPH

—

0.25

—

—

0.38

—

psRMS

—

1.7

2

Note 1: LVPECL applicable to automotive Grade 3 temperature only.

200 kHz to 20 MHz @ 156.25 MHz

100 kHz to 20 MHz @ 156.25 MHz

12 kHz to 20 MHz @ 156.25 MHz

2: See the Output Waveform section for more information.

3: The addition of IDDCORE and IDDIO provides the total current consumption of the device.

4: Period jitter includes crosstalk from adjacent output.

DS20006356A-page 6

 2020 Microchip Technology Inc.

Share Link: