ICE5QSAG データシートの表示（PDF） - Infineon Technologies

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ICE5QSAG

Quasi-Resonant Controller

Infineon Technologies 

Quasi-Resonant Controller

Functional Description

To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main power

switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the

gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time.

In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been

in high state longer than the maximum ON time, it will be turned off to prevent the switching frequency from

going too low because of long on time.

In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been

in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from

going too low because of long on time.

Also, if the voltage at the current sense pin is lower than the preset threshold VCS_STG after the time tCS_STG_SAM for

three consecutive pulses during on-time of the power switch, this abnormal VCS will trigger IC into auto restart

mode.

3.3.4

Modulated gate drive

The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the

CoolMOSTM turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 7).

Thus the leading switch spike during turn on is minimized.

VGATE (V)

VGATE_HIGH

typ. t = 117ns

5V

Figure 7 Gate rising waveform

t (ns)

3.4

Current limitation

There is a cycle by cycle current limitation realized by the current limit comparator to provide over-current

detection. The source current of the CoolMOS™ is sensed via a sense resistor RCS. By means of RCS the source

current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an internal

voltage limit, adjusted according to the Line voltage, the comparator immediately turns off the gate drive.

When the main bus voltage increases, the switch on time becomes shorter and therefore the operating

frequency is also increased. As a result, for a constant primary current limit, the maximum possible output

power is increased which is beyond the converter design limit.

To compensate such effect, both the internal peak current limit circuit (VCS) and the ZC count varies with the

bus voltage according to Figure 8.

Datasheet

10 of 27

V 2.1

2020-02-03

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