ICE5QSAG データシートの表示（PDF） - Infineon Technologies

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ICE5QSAG

Quasi-Resonant Controller

Infineon Technologies 

Quasi-Resonant Controller

Functional Description

MOSFET off-time according to the output power. In the following, the variation of the up/down counter value

according to the feedback voltage is explained.

The feedback voltage VFB is internally compared with three threshold voltages VFB_LHC, VFB_HLC and VFB_R at each

clock period of 48 ms. The up/down counter counts then upward, keep unchanged or count downward, as

shown in 0.

Table 3

Operation of up/down counter

VFB

up/down counter action

Always lower than VFB_LHC

Count upwards till n=8/101

Once higher than VF_LHC, but always lower than VFB_HLC

Stop counting, no value changing

Once higher than VFB_HLC, but always lower than VFB_R

Count downwards till n=1/32

Once higher than VFB_R

Set up/down counter to n=1/32

The number of zero crossing is limited and therefore, the counter varies among 1 to 8 (for low line) or 3 to 10

(for high line) and any attempt beyond this range is ignored. When VFB exceeds VFB_R voltage, the up/down

counter is reset to 1 (low line) and 3 (high line) in order to allow the system to react rapidly to a sudden load

increase. The up/down counter value is also reset to 1 (low line) and 3 (high line) at the start-up time, to ensure

an efficient maximum load start up. Figure 6 shows some examples on how up/down counter is changed

according to the feedback voltage over time.

The use of two different thresholds VFB_LHC and VFB_HLC to count upward or downward is to prevent frequency

jittering when the feedback voltage is close to the threshold point.

clock

T=48ms

clock

T=48ms

t

VFB

VFB,R1

VFB,HLC

VFB,LHC

Up/down

counter

t

1

Case 1 5 6 7 8 8 8 7 6 5 1

Case 2 2 3 4 5 5 5 4 3 2 1

Case 3 8 8 8 8 8 8 7 6 5 1

low line

Figure 6 Up/down counter operation

t

VFB

VFB,R3

VFB,HLC

VFB,LHC

Up/down

counter

t

3

Case 1 6 7 8 9 9 9 8 7 6 3

Case 2 4 5 6 7 7 7 6 5 4 3

Case 3 10 10 10 10 10 10 9 8 7 3

High line

3.3.1.3 Zero crossing (ZC counter)

In the system, the voltage from the auxiliary winding is applied to the ZCD pin through a RC network, which

provides a time delay to the voltage from the auxiliary winding. Internally this pin is connected to a clamping

network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller.

During on-state of the power switch, a positive gate drive voltage is applied to the ZCD pin due to RZCD resistor,

hence external diode DZC (see Figure 1) is added to block the negative voltage from the auxiliary winding. The ZC

counter has a minimum value of 1 (for low line) or 3 (for high line) and maximum value of 8 (for low line) or 10

1 n=8 (for low line) and n=10 (for high line)

2 n=1 (for low line) and n=3 (for high line)

Datasheet

8 of 27

V 2.1

2020-02-03

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