CLRC632 データシートの表示（PDF） - NXP Semiconductors.
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CLRC632 Datasheet PDF : 127 Pages
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NXP Semiconductors
7. Block diagram
CLRC632
Standard multi-protocol reader solution
NWR NRD NCS ALE
A0 A1 A2
AD0 to AD7/D0 to D7
10 11 9
21
22 23 24
13 14 15 16 17 18 19 20
PARALLEL INTERFACE CONTROL
(INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION)
FIFO CONTROL
STATE MACHINE
VOLTAGE
MONITOR
AND
POWER ON
DETECT
25
DVDD
12
DVSS
64-BYTE FIFO
COMMAND REGISTER
RESET
CONTROL
CONTROL REGISTER
BANK
PROGRAMMABLE TIMER
INTERRUPT CONTROL
POWER DOWN 31
CONTROL
2
RSTPD
IRQ
32 × 16-BYTE
EEPROM
EEPROM
ACCESS
CONTROL
CRC16/CRC8
GENERATION AND CHECK
PARALLEL/SERIAL CONVERTER
MASTER KEY BUFFER
BIT COUNTER
PARITY GENERATION AND CHECK
CRYPTO1 UNIT
FRAME GENERATION AND CHECK
BIT DECODING BIT ENCODING
32-BIT PSEUDO
RANDOM GENERATOR
SERIAL DATA SWITCH
3
MFIN
4
MFOUT
AMPLITUDE
RATING
REFERENCE
VOLTAGE
LEVEL SHIFTERS
CORRELATION
AND
BIT DECODING
I-CHANNEL
ANALOG
AMPLIFIER
TEST
MULTIPLEXER I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
Q-CHANNEL
DEMODULATOR
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
Q-CLOCK
GENERATION
1 OSCIN
OSCILLATOR
32
OSCOUT
POWER ON
DETECT
26
AVDD
28
AVSS
TRANSMITTER CONTROL
30
27
GND
V
GND
V
29
8
5
7
6
VMID
AUX
RX
TVSS TX1
TX2 TVDD 001aaj629
Fig 1. CLRC632 block diagram
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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