CLRC63201T データシートの表示（PDF） - NXP Semiconductors.

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CLRC63201T

Standard multi-protocol reader solution

NXP Semiconductors. 

NXP Semiconductors

CLRC632

Standard multi-protocol reader solution

9.1.3.2 Common read and write strobe

address bus (A3 to An)

ADDRESS

DECODER

DEVICE

NCS

address bus (A0 to A2)

data bus (D0 to D7)

HIGH

Data strobe (NDS)

Read/Write (R/NW)

A0 to A2

D0 to D7

ALE

NRD

NWR

non-multiplexed address

ADDRESS

DECODER

LOW

HIGH

LOW

multiplexed address/data (AD0 to AD7)

Address strobe (AS)

Data strobe (NDS)

Read/Write (R/NW)

Fig 4. Connection to microprocessor: common read and write strobes

DEVICE

NCS

A2

A1

A0

AD0 to AD7

ALE

NRD

NWR

001aak608

Refer to Section 13.4.2 on page 103 for timing specification.

9.1.3.3 Common read and write strobe: EPP with handshake

LOW

HIGH

HIGH

nWait

multiplexed address/data (AD0 to AD7)

Address strobe (nAStrb)

Data strobe (nDStrb)

Read/Write (nWrite)

DEVICE

NCS

A2

A1

A0

AD0 to AD7

ALE

NRD

NWR

001aak609

Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake

Refer to Section 13.4.3 on page 104 for timing specification.

Remark: In the EPP standard a chip select signal is not defined. To cover this situation,

the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not

used, it is mandatory that pin NCS is connected to pin DVSS.

Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is

high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after

the reset phase. The CLRC632 does not support Read Address Cycle.

9.1.4 Serial Peripheral Interface

The CLRC632 provides compatibility with the 5-wire Serial Peripheral Interface (SPI)

standard and acts as a slave during the SPI communication. The SPI clock signal SCK

must be generated by the master. Data communication from the master to the slave uses

the MOSI line. The MISO line sends data from the CLRC632 to the master.

CLRC632

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.7 — 27 February 2014

073937

© NXP Semiconductors N.V. 2014. All rights reserved.

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