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BR24G04FVM-3E2(2013) データシートの表示(PDF) - ROHM Semiconductor

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BR24G04FVM-3E2
(Rev.:2013)
ROHM
ROHM Semiconductor ROHM
BR24G04FVM-3E2 Datasheet PDF : 37 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
BR24G04-3
Block Diagram
A0 1
A1 2
14KKbbit~it25E6EKPbiRt OEEMPRaOrrMayarray
8bit
Address
Decoder
Word Address
9bit
Register
Data
Register
A2 3
GND 4
START
Control circuit
STOP
ACK
High Voltage
Generating Circuit
Power Source
Voltage Detection
8 VCC
7 WP
6 SCL
5 SDA
Figure 3. Block Diagram
Datasheet
Pin Configuration
(TOP VIEW)
A0
1
A1
2
A2
3
BR24G04-3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
Pin Descriptions
Terminal
Name
A0
A1
A2
Input/
Output
-
Input
Input
Descriptions
Don’t use(1)
Slave address setting(2)
Slave address setting(2)
GND
SDA
SCL
-
Input/
output
Input
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
WP
Input Write protect terminal
VCC
-
Connect the power source.
(1) Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
(2) A1 and A2 are not allowed to use as open.
www.rohm.com
©2013 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/33
TSZ02201-0R2R0G100180-1-2
31.May.2013 Rev.003

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