BR24G04FJ-3A データシートの表示（PDF） - ROHM Semiconductor

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BR24G04FJ-3A

Serial EEPROM series Standard EEPROM I2C BUS EEPROM (2-Wire)

ROHM Semiconductor 

BR24G04-3A

●Serial Input / Output timing

tR

tF1

tHIGH

SCL

tHD:STA

70%

70% 70%

30%

30%

tSU:DAT

tLOW

70%

30%

70%

30%

tHD:DAT

70%

70%

70%

SDA

(INP(入U力 T))

SDA

(outpuStD) A

(OUTP(出 UT力) )

30%

tBUF

tPD

70%

30%

70%

30%

tDH

70%

30%

30%

70%

30%

○ Input read at the rise edge of SCL

○ Data output in sync with the fall of SCL

70%

30%

tF2

Figure 2-(a). Serial input / output timing

70%

70%

70%

tSU:STA

tHD:STA

tSU:STO

70%

30% 30%

30%

30%

STARSTTACROTNDCITOINODNITION

STOP COSTNODPITICOONNDITION

Figure 2-(b). Start-stop bit timing

D0

write data

(n-th address)

ACK

70%

70%

tWR

STOP CONDITION START CONDITION

Figure 2-(c). Write cycle timing

70%

DATA(1)

D1

D0 ACK

DATA(n)

ACK

70%

tWR

30%

tSU:WP

tSU:WP

30%

tHD:WP

STtHODP:WCOPNDITION

STOP CONDITION

Figure 2-(d). WP timing at write execution

DATA(1)

DATA(n)

D1DATA(D1)0 ACK

DATA(n)

D1 D0 ACK

tHIGH:WP

tHIGH:WP

70%

70%

Fig1-(4) Write70c%ycle tim7i0n%g

ACK

ACK

70%

70%

tWR

tWR

Fig1-(5) FWigPurteim2in-(ge)a.tWwPrittiemienxgeactuwtiorinte cancel

Fig1-(6) WP timing at write cancel

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TSZ22111 • 15 • 001

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TSZ02201-0R2R0G100560-1-2

11.Jun.2019 Rev.004

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