BR24T04FVJ-WG_ データシートの表示（PDF） - ROHM Semiconductor
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BR24T04FVJ-WG_ Datasheet PDF : 22 Pages
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BR24T□□□□Series
Technical Note
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a
command to read data by designating address, and is used generally. Current read cycle is a command to read data of
internal address register without designating address, and is used when to verify just after write cycle. In both the read
cycles, sequential read cycle is available, and the next address data can be read in succession.
S
W
T
R
A
I
R
SLAVE
T
T ADDRESS E
WORD
ADDRESS(n)
S
T
R
A
E
R
SLAVE
A
T ADDRESS D
S
T
O
DATA(n)
P
SDA
LINE
1 0 1 0 A2A1A0
WA
7
WA
0
1 0 1 0 A2A1A0 D7
*1 As for WA7,BR24T01-W become Don’t care.
D0
R A *1
A
RA
A
Note)
/C
WK
C
K
/C
WK
C
K
Fig.43 Random read cycle (BR24T01/02/04/08/16-W)
SDA
LINE
S
W
T
R
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS
（）
1 0 1 0 A2 A1 A0
WAWAWAWAWA
15 14 13 12 11
S
T
R
S
2nd WORD
ADDRESS(n)
A
R
T
SLAVE
ADDRESS
E
A
D
DATA(n)
T
O
P
WA
0
1 0 1 0 A2 A1A0
D7
D0
RA
Note)
/C
*1
A
C
A
RA
C
/C
A
C
WK
K
K
WK
K
Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)
*1 As for WA12, BR24T32-W become Don’t care.
As for WA13, BR24T32/64-W become Don’t care.
As for WA14, BR24T32/64/128-W become Don’t care.
As for WA15, BR24T32/64/128/256-W become Don’t care.
SDA
LINE
S
T
R
A
E
R SLAVE
A
T ADDRESS D
1 0 1 0 A2A1A0
S
T
O
DATA(n)
P
D7
D0
*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)
RA
A
Note)
/C
WK
C
K
Fig.45 Current read cycle
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1A0
D7
DATA(n)
D0
S
T
DATA(n+x)
O
P
D7
D0
RA
A
A
A
Note）
/C
WK
C
K
C
K
C
K
Fig.46 Sequential read cycle (in the case of current read cycle)
*1 As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL
signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A2 A1A0
*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T08/16/1M-W, A0 becomes P0.
Fig.47 Difference of slave address of each type
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11/21
2011.03 - Rev.A
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