ADSQ-1410 データシートの表示（PDF） - Murata Power Solutions
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ADSQ-1410 Datasheet PDF : 11 Pages
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For applications that require small full scale input ranges less sensitiv-
ity may be required for offset adjustment. In this case an external series
resistor can be added with the internal 20.5kΩ resistor on the OFFSET ADJ
pin. In this case the Offset Voltage can be calculated by:
Eq. 4:
Voffset = 2 Range (Codes)
487.9
(Rexternal + 20500)
Where: RANGE = the RANGE pin voltage
Codes = Desired offset adjustment range
Rexternal = External Offset series resistor
ADSQ-1410
Quad 14-Bit, 10 MSPS Sampling A/D Converter
Typical for AB & CD Output Bus
A/D_ A
Buffer_A
A/D_ B
Buffer_B
EN_A
AB Output Bus &
Overflow
(pins 54-66 & 20)
OFFSET ADJ
VIN ±2.5V
SGND
20.5k
470
470
To A/D
Input
Section
ADSQ-1410 Quad Input Stage
DIGITAL OUTPUT AND TIMING
The ADSQ-1410 is configured such that the output bits and overflow for
channels A&B are multiplexed on the AB Output Bus (pins 54 - 66 & 20)
and channels C&D are similarly multiplexed on the CD Output Bus (pins
34-47 & 21). See the Output Block Diagram figure. The output drivers are
designed to conveniently operate from VDD = +2V to +5V and are capable
of sinking and sourcing up to 4mA of current. However, switching large
drive currents can cause glitches on the supplies that could couple into
and create disturbances on an ongoing A/D conversion affecting the SINAD
and SNR performance. Applications where high drive current is required
may require additional supply voltage bypassing or external digital buffers.
The EN_ pins are used to select the appropriate output data. EN_ control
pins are active LO (HI= high-z). Caution must be exercised to assure that
both channels on the same bus are not enabled at the same time. Each
data bus of the ADSQ-1410 is capable of providing data throughput at a
20MHz rate. See Enable and Disable timing diagrams and table.
Input logic levels for EN_ pins are dictated by +VDD supply voltage; logic
level for START_CONV is a function of +5V supply. See Functional Specifi-
cations: Digital Inputs.
EN_B
Output Block Diagram
Parameter
Start Conv Period
Start Conv Pulse High
Start Conv Pulse Low
Output Delay
Symbol Min Typ Max Unit
tc
100
1x106
ns
tch
45
ns
tcl
45
ns
tod
13
18
27
ns
Table 1. Digital Output And Timing
ANALOG
INPUT
START
CONV
N
N+1
tC
t CH t CL
N+2
DATA
OUTPUT
Data N-3
Data N-2
Data N-1
(Enable Pin = LO)
ADSQ-1410 Timing Diagram
t OD
Data N
Parameter
Hi-Z to Active HI
Hi-Z to Active LO
Active HI to Hi-Z
Active LO to Hi-Z
Symbol
t-pZH
t-pZL
t-pHZ
t-pLZ
Typ
6.6ns
6.6ns
7.8ns
7.8ns
Max
10.6ns
10.6ns
11.5ns
11.5ns
Table 2. Enable and Disable Times
NOTE: Outputs are enabled when ENABLE pins = LO (Hi-Z = HI). Caution must
be taken to assure that shared outputs are not enabled at the same time.
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Technical enquiries email: data.acquisition@murata-ps.com, tel: +1 508 339 3000
MDA_ADSQ.B01 Page 4 of 11
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