MAX793TCSE データシートの表示（PDF） - Maxim Integrated
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MAX793TCSE Datasheet PDF : 20 Pages
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3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RESET Output-Voltage Low
VOL
MAX79_C, VBATT = VCC = 1.0V, ISINK = 40µA
MAX79_E, VBATT = VCC = 1.2V, ISINK = 200µA
BATT ON Output-
Voltage Low
VOL ISINK = 3.2mA, VCC = VRST max
0.13
0.3
V
0.17
0.3
0.2VCC V
All Inputs Including PFO
(Note 10)
MANUAL RESET INPUT
MR Pulse Width
MR-to-Reset Delay
MR Pullup Current
VIH
VIL
VRST max < VCC < 5.5V
tMR MAX793/MAX794 only
tMD MAX793/MAX794 only
MAX793/MAX794 only, MR = 0V
0.3VCC
0.7VCC
V
100
ns
75
250
ns
25
70
250
µA
CHIP-ENABLE GATING
CE IN Leakage Current
CE IN-to-CE OUT
Resistance
ILEAK
Disable mode
Enable mode, VCC = VRST max
±10
nA
46
Ω
CE IN-to-CE OUT
Propagation Delay
VCC = VRST max, Figure 9
2
7
ns
VOH
CE OUT Drive from CE IN
VOL
Reset to CE OUT High Delay
CE OUT Output-Voltage
High (reset active)
VOH
VCC = VRST max, IOUT = -1mA,
V CE IN = VCC
VCC = VRST max, IOUT = 1.6mA,
V CE IN = 0V
IOH = 500µA, VCC < 2.3V
0.8VCC
10
0.8VBATT
V
0.2VCC
µs
V
WATCHDOG (MAX793/MAX794 only)
WDI Input Current
Watchdog Timeout Period
WDI Pulse Width
0V < VCC < 5.5V
tWD
-1
0.01
1
µA
1.00
1.60
2.25
s
100
ns
Note 1: VCC supply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at VBATT = 3.6V and VCC =
5.5V. The state of RESET is tested at VCC = VCC min.
Note 2: Tested at VBATT = 3.6V, VCC = 3.5V and 0V. The battery current rises to 10µA over a narrow transition window around VCC
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at VCC = 5.5V, VBATT = 1.8V and VCC = 1.5V,
VBATT = 1.0V.
Note 4: Guaranteed by design.
Note 5: When VSW > VCC > VBATT, OUT remains connected to VCC until VCC drops below VBATT. The VCC-to-VBATT comparator
has a small 15mV typical hysteresis to prevent oscillation. For VCC < 1.75V (typical), OUT switches to BATT regardless of
VBATT.
Note 6: When VBATT > VCC > VSW, OUT remains connected to VCC until VCC drops below the battery switch threshold (VSW).
Note 7: OUT switches from BATT to VCC when VCC rises above the reset threshold, if VBATT > VRST. In this case, switchover back
to VCC occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If
VBATT < VRST, OUT switches from BATT to VCC when VCC exceeds VBATT.
Note 8: The reset threshold tolerance is wider for VCC rising than for VCC falling to accommodate the 10mV typical hysteresis,
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
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