LTC693IN データシートの表示（PDF） - Linear Technology

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LTC693IN

Microprocessor Supervisory Circuits

Linear Technology 

LTC692/LTC693

APPLICATIONS INFORMATION

If battery connections are made through long wires, a

10Ω to 100Ω series resistor and a 0.1μF capacitor are

recommended to prevent any overshoot beyond VCC due

to the lead inductance (Figure 4).

Table 1 shows the state of each pin during battery backup.

When the battery switchover section is not used, connect

VBATT to GND and VOUT to VCC.

10Ω

3.9M

VBATT

0.1μF

LTC692

LTC693

GND

692_3 • F04

Figure 4. 10Ω/0.1μF Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery

Replacement

Memory Protection

The LTC693 includes memory protection circuitry which

ensures the integrity of the data in memory by preventing

write operations when VCC is at an invalid level. Two ad-

ditional pins, CE IN and CE OUT, control the Chip Enable

or Write inputs of CMOS RAM. When VCC is 5V, CE OUT

follows CE IN with a typical propagation delay of 20ns.

When VCC falls below the reset voltage threshold or VBATT,

CE OUT is forced high, independent of CE IN. CE OUT is

an alternative signal to drive the CE, CS, or Write input of

Table 1. Input and Output Status in Battery Backup Mode

SIGNAL STATUS

VCC

VOUT

VBATT

BATT ON

PFI

PFO

RESET

C2 monitors VCC for active switchover

VOUT is connected to VBATT through an internal PMOS switch

The supply current is 1μA maximum

Logic high. The open-circuit output voltage is equal to VOUT

Power failure input is ignored

Logic low

Logic low

RESET Logic high. The open-circuit output voltage is equal to VOUT

LOW LINE Logic low

WDI

WDO

CE IN

CE OUT

OSC IN

Watchdog input is ignored

Logic high. The open-circuit output voltage is equal to VOUT

Chip Enable input is ignored

Logic high. The open-circuit output voltage is equal to VOUT

OSC IN is ignored

OSC SEL OSC SEL is ignored

battery backed up CMOS RAM. CE OUT can also be used

to drive the Store or Write input of an EEPROM, EAROM

or NOVRAM to achieve similar protection. Figure 5 shows

the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address

decoder output. Figure 6 shows a typical nonvolatile CMOS

RAM application.

Memory protection can also be achieved with the LTC692

by using RESET as shown in Figure 7.

V2

VCC

V1

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

CE IN

CE OUT

VOUT = VBATT

Figure 5. Timing Diagram for CE IN and CE OUT

VOUT = VBATT

692_3 • F05

0692fa

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