MAX822 データシートの表示（PDF） - Maxim Integrated

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MAX822

4-Pin µP Voltage Monitors with Pin-Selectable Power-On Reset Timeout Delay

Maxim Integrated 

4-Pin µP Voltage Monitors with Pin-Selectable

Power-On Reset Timeout Delay

Ensuring a Valid RESET Output

Down to VCC = 0V

When VCC falls below 1V, the MAX821 RESET output

no longer sinks current—it becomes an open circuit.

Therefore, high-impedance CMOS logic inputs con-

nected to the RESET output can drift to undetermined

voltages. This presents no problem in most applica-

tions, since most µP and other circuitry is inoperative

with VCC below 1V. However, in applications where the

RESET output must be valid down to 0V, adding a pull-

down resistor to the RESET pin will cause any stray

leakage currents to flow to ground, holding RESET low

(Figure 2a). R1’s value is not critical; 100kΩ is large

enough not to load RESET, and small enough to pull

RESET to ground.

A 100kΩ pull-up resistor to VCC is also recommended

for the MAX822 if RESET is required to remain valid for

VCC < 1V (Figure 2b).

Interfacing to µPs with

Bidirectional Reset Pins

µPs with bidirectional reset pins (such as the Motorola

68HC11 series) can contend with the MAX821 reset

output. For example, if the MAX821 RESET output is

asserted high and the µP wants to pull it low, indetermi-

nate logic levels may result. To correct such cases,

connect a 4.7kΩ resistor between the MAX821 RESET

output and the µP reset I/O (Figure 3). Buffer the reset

output to other system components.

___________________Chip Information

TRANSISTOR COUNT: 492

VCC

VCC

VCC

MAX821

RESET

R1

GND

a)

VCC

R1

MAX822

RESET

GND

b)

Figure 2. RESET/RESET Valid to VCC = Ground Circuit

VCC

MAX821

4.7k

RESET

GND

BUFFER

BUFFERED RESET

TO OTHER SYSTEM

COMPONENTS

VCC

µP

RESET

GND

Figure 3. Interfacing to µPs with Bidirectional Reset I/O

6 _______________________________________________________________________________________

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