LTC1325CN データシートの表示（PDF） - Linear Technology
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LTC1325CN Datasheet PDF : 24 Pages
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LTC1325
ELECTRICAL CHARACTERISTICS VDD = 12V ±5%, TA = 25°C, unless otherwise noted.
SYMBOL PARAMETER
VOL
Output Low Voltage
VOH
Output High Voltage
IOZ
Hi-Z Output Leakage
VOHFET
DIS or PGATE Output High
VOLFET
DIS or PGATE Output Low
tdDO
Delay Time, CLK↓ to DOUT Valid
tdis
Delay Time, CS↑ to DOUT Hi-Z
ten
Delay Time, CLK↓ to DOUT Enabled
thDO
Time DOUT Remains Valid After CLK↓
trDOUT
DOUT Rise Time
tfDOUT
DOUT Fall Time
fCLK
Serial I/O Clock Frequency
trPGATE
PGATE Rise Time
tfPGATE
PGATE Fall Time
fOSC
Internal Oscillator Frequency
A/D Converter
Offset Error
Linearity Error
Full-Scale Error
On-Channel Leakage
Off-Channel Leakage
CONDITIONS
DOUT, IOUT = 1.6mA
DOUT, IOUT = – 1.6mA
VCS = 5V
VDD = 4.5V to 16V
VDD = 4.5V to 16V
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
See Test Circuits
CLK Pin
CLOAD = 1500pF
CLOAD = 1500pF
Charge Mode, Fail-Safes Disabled
VIN Channel (Note 3)
VIN Channel (Notes 3, 4)
VIN Channel (Note 3)
VIN Channel ON Only (Notes 3, 5)
VIN Channel OFF (Notes 3, 5)
MIN TYP MAX
q
0.4
q
2.4
q
±10
q VDD – 0.05
q
0.05
q
650
q
510
q
400
q
30
q
250
q
100
q
25
500
q
150
q
150
90
111 130
q
±2
q
±0.5
q
±1
q
±10
q
±10
UNITS
V
V
µA
V
V
ns
ns
ns
ns
ns
ns
kHz
ns
ns
kHz
LSB
LSB
LSB
µA
µA
RECO E DED CHARACTERISTICS
SYMBOL
thDI
tdsuCS
tdsuDI
tWHCLK
tWLCLK
tWHCS
tWLCS
PARAMETER
Hold Time, DIN After CLK↑
Setup Time, CS Before First CLK↑
Setup Time, DIN Stable Before First CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfers
CS Low Time During Data Transfer
CONDITIONS
MSBF = 1
MSBF = 0
MIN TYP MAX
UNITS
150
ns
1
µs
400
ns
0.8
µs
1
µs
1
µs
43
CLK Cycles
52
CLK Cycles
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to the GND pin.
Note 3: VREG within specified min and max limits, CLK (Pin 5) = 500kHz,
unless otherwise stated. ADC clock is the serial CLK.
Note 4: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 5: Channel leakage is measured after channel selection.
Note 6: Gas gauge offset excludes A/D offset error.
Note 7: I = VDAC(Duty Ratio)/RSENSE, where VDAC is the DAC output
voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and RSENSE is
determined by the user.
3
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