AD664AD(RevC) データシートの表示（PDF） - Analog Devices

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AD664AD
(Rev.:RevC)

Monolithic 12-Bit Quad DAC

Analog Devices 

AD664

occupies the topmost eight bits of the input word. The last four

bits of the input word are “don’t cares.”

Figure 15 shows the format of the MODE SELECT word. The

first four bits determine the gain range of the DAC. When set to

be a gain of 1, the output of the DAC spans a voltage of 1 times

the reference. When set to a gain of 2, the output of the DAC

spans a voltage of 2 times the reference.

The next four bits determine the mode of the DAC. When set to

UNIPOLAR, the output goes from 0 to REF or 0 to 2 REF.

When the BIPOLAR mode is selected, the output goes from

–REF/2 to REF/2 or –REF to REF.

Preloading the Mode Select Register

Mode data can be written into the first rank of the mode select

latch without changing the modes currently being used. This

feature is useful when a user wants to preload new mode infor-

mation in anticipation of strobing that in at a future time. Fig-

ure 17 illustrates the correct sequence and timing of control

signals to accomplish this task.

This allows the user to “preload” the data to a DAC and strobe

it into the output latch at some future time. The user could do

this by reproducing the sequence of signals illustrated in Figures

17c and 17d.

Figure 15. Mode Select Word Format

Load and Update Mode of One DAC

In this next example, the object is to load new mode informa-

tion for one of the DACs into the first rank of latches and then

immediately update the second rank. This is done by putting the

new mode information (8-bit word length) onto the databus.

Then MS and LS are pulled low. Following that, CS is pulled

low. This loads the mode information into the first rank of

latches. LS is then brought high. This action updates the second

rank of latches (and, therefore, the DAC outputs). The load

cycle ends when CS is brought high.

In reality, this load cycle really updates the modes of all the

DACs, but the effect is to only change the modes of those

DACs whose mode select information has actually changed.

Figure 16a. Load and Update Mode of One DAC

SYMBOL

25؇C

MIN (ns)

TMIN to TMAX

MIN (ns)

tMS

0

0

tLS*

0

0

tDS

0

0

tLW

60

70

tCH

70

80

tDH

0

0

tMH

0

0

*FOR tLS > 0, THE WIDTH OF LS MUST BE

INCREASED BY THE SAME AMOUNT THAT

tLS IS GREATER THAN 0 ns.

Figure 16b. Load and Update Mode of One DAC Timing

Figure 17a. Preload Mode Select Register

Figure 17b. Preload Mode Select Register Timing

DATA

1

INPUT/OUTPUT

BITS

0

__A_DD__R_ES_S__ 1

QS0,QS1,QS2

DS0,DS1

0

__

MS

__ t MS

CS

t MH

tW

Figure 17c. Update Second Rank of Mode Select Latch

SYMBOL

tMS

tMH

tW

25؇C

MIN (ns)

0

0

80

TMIN to TMAX

MIN (ns)

0

0

100

Figure 17d. Update Second Rank of Mode Select Latch

Timing

Transparent Operation (44-Pin Versions)

Transparent operation allows data from the inputs of the

AD664 to be transferred into the DAC registers without the

intervening step of being latched into the first rank of latches.

Two modes of transparent operation exist, the “partially trans-

parent” mode and a “fully transparent” mode. In the “partially

transparent” mode, one of the DACs is transparent while the

remaining three continue to use the data latched into their

respective input registers. Both modes require a 12-bit wide

input word!

–10–

REV. C

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