STLC5465 データシートの表示（PDF） - STMicroelectronics

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STLC5465

MULTI - HDLC WITH N X 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5465B

I - PIN INFORMATION (continued)

I.2 - Pin Description (continued)

Pin N°

Symbol

Type

Function

MICROPROCESSOR INTERFACE (continued)

51

SIZE0/NLDS

I3 Transfer Size0 (68020)/Lower Data Strobe (68000)

52 SIZE1/NBHE/NUDS I3 Transfer Size1 (68020)/Bus High Enable (Intel) / Upper Data Strobe (68000)

53 NDSACK0/NDTACK O8T Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge

(68000)

54 NDSACK1/READY O8T Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge

(Intel)

55

NAS/ALE

I3 Address Strobe(Motorola) / Addresss Latch Enable(Intel)

56

R/W / NWR

I3 Read/Write (Motorola / Write(Intel)

57

NDS/NRD

I3 Data Strobe (Motorola 68020); at Vdd for 68000/Read Data (Intel)

63

A0/AD0

I/O Address bit 0 (Motorola 68020); at Vdd for 68000 / Address/Data bit 0 (Intel)

64

A1/AD1

I/O Address bit 1 (Motorola) / Address/Data bit 1 (Intel)

65

A2/AD2

I/O Address bit 2 (Motorola) / Address/Data bit 2 (Intel)

66

A3/AD3

I/O Address bit 3 (Motorola) / Address/Data bit 3 (Intel)

67

A4/AD4

I/O Address bit 4 (Motorola) / Address/Data bit 4 (Intel)

68

A5/AD5

I/O Address bit 5 (Motorola) / Address/Data bit 5 (Intel)

69

A6/AD6

I/O Address bit 6 (Motorola) / Address/Data bit 6 (Intel)

70

A7/AD7

I/O Address bit 7 (Motorola) / Address/Data bit 7 (Intel)

71

A8/AD8

I/O Address bit 8 (Motorola) / Address/Data bit 8 (Intel)

72

A9/AD9

I/O Address bit 9 (Motorola) / Address/Data bit 9 (Intel)

75

A10/AD10

I/O Address bit 10 (Motorola) / Address/Data bit 10 (Intel)

76

A11/AD11

I/O Address bit 11 (Motorola) / Address/Data bit 11 (Intel)

77

A12/AD12

I/O Address bit 12 (Motorola) / Address/Data bit 12 (Intel)

78

A13/AD13

I/O Address bit 13 (Motorola) / Address/Data bit 13 (Intel)

79

A14/AD14

I/O Address bit14 (Motorola) / Address/Data bit 14 (Intel)

80

A15/AD15

I/O Address bit15 (Motorola) / Address/Data bit 15 (Intel)

81

A16

I1 Address bit16 (Motorola) / Address bit 16 (Intel)

82

A17

I1 Address bit17 (Motorola) / Address bit 17 (Intel)

83

A18

I1 Address bit18 (Motorola) / Address bit 18 (Intel)

84

A19

I1 Address bit19 (Motorola) / Address bit 19 (Intel)

85

A20/ADM15

I/O Address bit 20 from µP (input) / Address bit 15 for SRAM (output)

86

A21/ADM16

I/O Address bit 21 from µP (input) / Address bit 16 for SRAM (output)

87

A22/ADM17

I/O Address bit 22 from µP (input) / Address bit 17 for SRAM (output)

88

A23/ADM18

I/O Address bit 23 from µP (input) / Address bit 18 for SRAM (output)

91

DO

I/O Data bit 0 for µP if not multiplexed (see Note 1).

92

D1

I/O Data bit 1 for µP if not multiplexed

93

D2

I/O Data bit 2 for µP if not multiplexed

94

D3

I/O Data bit 3 for µP if not multiplexed

95

D4

I/O Data bit 4 for µP if not multiplexed

96

D5

I/O Data bit 5 for µP if not multiplexed

97

D6

I/O Data bit 6 for µP if not multiplexed

98

D7

I/O Data bit 7 for µP if not multiplexed

99

D8

I/O Data bit 8 for µP if not multiplexed

Type : I1 = Input TTL ;

I2 = I1 + Pull-up ;

O4 = Output CMOS 4mA ;

O4T = O4 + Tristate ;

O8D = Output CMOS 8mA, Open Drain ;

O8T = Output CMOS 8mA, Tristate

I3 = I1 + Hysteresis ;

I4 = I3 + Pull-up ;

O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;

O8DT = Output CMOS 8mA, Open Drain or Tristate ;

11/101

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