SST32HF802-70-4E-EK データシートの表示（PDF） - Silicon Storage Technology
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SST32HF802-70-4E-EK Datasheet PDF : 28 Pages
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
6
BES# VSS DQ1 A1 A2 A4 NC A9
5
A10 DQ5 DQ2 A0 A3 A7 NC A14
4
OE# DQ7 DQ4 DQ0 A6 A18 NC A15
3
A11 A8 A5 DQ8 DQ3 DQ12 A12 LBS#
2
A13 A17 UBS# BEF# DQ10 VDDF DQ6 DQ15
1
WE# VDDS A16 VSS DQ9 DQ11 DQ13 DQ14
6
BES# VSS DQ1 A1 A2 A4 A19 A9
5
A10 DQ5 DQ2 A0 A3 A7 NC A14
4
OE# DQ7 DQ4 DQ0 A6 A18 NC A15
3
A11 A8 A5 DQ8 DQ3 DQ12 A12 LBS#
2
A13 A17 UBS# BEF# DQ10 VDDF DQ6 DQ15
1
WE# VDDS A16 VSS DQ9 DQ11 DQ13 DQ14
ABCDEFGH
SST32HF802
ABCDEFGH
SST32HF162/SST32HF164
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TBGA (10MM X 12MM)
TABLE 2: PIN DESCRIPTION
Symbol Pin Name
AMS1-A0 Address Inputs
DQ15-DQ0 Data Input/output
BES#
BEF#
OE#
WE#
VDDF
VDDS
SRAM Memory Bank Enable
Flash Memory Bank Enable
Output Enable
Write Enable
Power Supply (Flash)
Power Supply (SRAM)
VSS
UBS#
LBS#
NC
Ground
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
No Connection
1. AMS=Most significant address
Functions
To provide flash addresses: A19-A0 for 16M, and A18-A0 for 8M
SRAM addresses: A16-A0 for 2M and A17-A0 for 4M
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
To activate the SRAM memory bank when BES# is low.
To activate the Flash memory bank when BEF# is low.
To gate the data output buffers.
To control the Write operations.
2.7-3.3V Power Supply to Flash only.
2.7-3.3V Power Supply to SRAM only
(For L3K package, VDDF and VDDS share one pin as VDD.)
To enable DQ15-DQ8
To enable DQ7-DQ0
Unconnected Pins
T2.2 520
©2001 Silicon Storage Technology, Inc.
6
S71171-05-000 8/01 520
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