XRT4500 データシートの表示（PDF） - Exar Corporation

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XRT4500

MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

Exar Corporation 

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PIN DESCRIPTIONS

XRT4500

MULTIPROTOCOL SERIAL NETWORK INTERFACE IC

REV. 1.0.5

PIN

Signal

#

DTE

MODE

DCE TYPE FUNCTION

MODE

1

RX1D

D_RXD D_TXD O Receiver 1 Digital Output – Digital Data Output to terminal

equipment

This output pin is the digital (TTL/CMOS level) representation of

the line signal that has been received via the RX1A (pin 78) and

RX1B (pin 79) input pins.

The exact role that this pin plays depends upon whether the

XRT4500 is operating in the DCE or DTE Mode.

DCE Mode – TXD Digital Output Signal

This output pin functions as the TXD Digital Output signal (which

should be input to the Terminal Equipment).

2

VDD

3

GND

4

M0

DTE Mode – RXD Digital Output Signal

This output pin functions as the RXD Digital Output signal (which

should be input to the Terminal Equipment).

Analog VDD for Receiver 1, 2, 3

I Analog GND for Receiver 1, 2, 3 and Transmitter 3

I Mode Control – Mode Select Input 0

This input pin, along with M1 and M2 are used to configure the

XRT4500 to operate in the desired “Communication Interface”

Mode. Table 3 and Table 4 present the relationship between

the states of the M2, M1 and M0 input pins and the correspond-

ing communication interface modes selected.

This input pin (along with M1 and M2) is internally latched into

the XRT4500, upon the rising edge of the “LATCH” signal. At this

point, changes in this input pin will not effect the “internally

latched” state of this pin.

5

M1

This input pin contains an Internal 20KΩ pull-up to VDD.

I Mode Control – Mode Select Input 1

This input pin, along with M0 and M2 are used to configure the

XRT4500 to operate in the desired “Communication Interface”

Mode. Table 3 and Table 4 present the relationship between the

states of the M2, M1 and M0 input pins and the corresponding

communication interface modes selected.

This input pin (along with M0 and M2) is internally latched into the

XRT4500 device, upon the rising edge of the “LATCH” signal. At

this point, changes in this input pin will not effect the “internally

latched” state of this pin.

This input pin contains an Internal 20KΩ pull-up to VDD.

4

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