AD9841A データシートの表示（PDF） - Analog Devices

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AD9841A

Complete 20 MSPS CCD Signal Processors

Analog Devices 

AD9841A/AD9842A

CCD-MODE AND AUX MODE TIMING

CCD

SIGNAL

N

N+1

N+2

N+9

tID

tID

SHP

tS1

tS2

tCP

SHD

tINH

DATACLK

tOD

tH

OUTPUT

N–10

N–9

N–8

N–1

DATA

NOTES:

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 5. CCD-Mode Timing

N+10

N

CCD

SIGNAL

EFFECTIVE PIXELS

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS

EFFECTIVE PIXELS

CLPOB

CLPDM

PBLK

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

DUMMY BLACK

EFFECTIVE DATA

NOTES:

1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.

Figure 6. Typical CCD-Mode Line Clamp Timing

VIDEO

SIGNAL

DATACLK

OUTPUT

DATA

N

N+1

N+9

N+8

tID

N+2

tCP

tOD

N–10

tH

N–9

N–8

N–1

N

Figure 7. AUX-Mode Timing

–10–

REV. 0

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