MC14560BD データシートの表示（PDF） - Motorola => Freescale

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MC14560BD

NBCD Adder

Motorola => Freescale 

SUMMARY

The concepts of binary code representations for decimal

numbers, addition, and complement subtraction were dis-

cussed in detail. Using the basic Adder and Complementer

MSI blocks, adder/subtracters for both signed and unsigned

numbers were illustrated with examples.

REFERENCES

1. Chu, Y.: Digital Computer Design Fundamentals, New

York, McGraw–Hill, 1962.

2. McMOS Handbook, Motorola Inc., 1st Edition.

3. Beuscher, H.: Electronic Switching Theory and Circuits,

New York, Van Nostrand Reinhold, 1971.

4. Garrett, L.: CMOS May Help Majority Logic Win De-

signer’s Vote, Electronics, July 19, 1973.

5. Richards, R.: Digital Design, New York, Wiley–

Interscience, 1971.

A1

B1

LSD

Cin BASIC Cout

SUBTRACT

C BLOCK

A2

Cin

C

B2

An

MSD

Cout

Cin

C

Bn

Cout

R1

R2

Rn

ADD/SUBTRACT

(“1”/“0”)

1/6 MC14572

OVERFLOW = “1”

1/6 MC14572

UNDERFLOW = “1”

(NEGATIVE RESULT)

Typical Add/Subtract Time = 0.6 + 0.4 n µs

where n = Number of Decades

Figure 7. Adder/Subtracter for Unsigned NBCD Numbers

MC14560B

8

MOTOROLA CMOS LOGIC DATA

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