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ICS650R-07(V2) データシートの表示(PDF) - Integrated Circuit Systems

部品番号
コンポーネント説明
メーカー
ICS650R-07
(Rev.:V2)
ICST
Integrated Circuit Systems ICST
ICS650R-07 Datasheet PDF : 4 Pages
1 2 3 4
Pin Assignment
PS 1
X2 2
X1/ICLK 3
VDD 4
DC 5
GND 6
125M 7
125M 8
DC 9
133M 10
20 VDD
19 VDD
18 25M
17 PCICLK
16 VDD
15 OE
14 GND
13 D C
12 D C
11 GND
20 pin (150 mil) SSOP
ICS650-07B
Broadcom Clock Source
PCI CLK Output Select Table
PS
Pin 1
0
1
PCICLK
Pin 17
33.33 MHz
66.66 MHz
0 = connect directly to GND
1 = connect directly to VDD
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
PS
X2
X1/ICLK
VDD
DC
GND
125M
125M
DC
133M
GND
DC
DC
GND
OE
VDD
PCICLK
25M
VDD
VDD
Type
I
XO
XI
P
-
P
O
O
-
O
P
-
-
P
I
P
O
O
P
P
Description
PCI Clock frequency select input. Determines PCI CLK output per table above.
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Don't Connect. Do not connect anything to this pin.
Connect to ground.
125.0 MHz clock output. Cannot be used for Gigabit Ethernet SERDES.
125.0 MHz clock output. Cannot be used for Gigabit Ethernet SERDES.
Don't Connect. Do not connect anything to this pin.
133.33 MHz clock output.
Connect to ground.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Connect to ground.
Output Enable. Tri-states all outputs when low. Internal pull-up.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
PCI Clock output per table above.
25.0 MHz buffered reference clock output.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Key: XI, XO = crystal connections; I = Input; O = Output; P = power supply connection
MD S 650-07B A
2
Revision 042600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

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