ICS650-07C データシートの表示（PDF） - Integrated Circuit Systems
部品番号
コンポーネント説明
メーカー
ICS650-07C Datasheet PDF : 5 Pages
| |||
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5 V
Ambient Operating Temperature
0
70
°C
Ambient Operating Temperature, I version
Industrial temp
-40
85
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage temperature
-65
DC CHARACTERISTICS (VDD = 5.0V unless noted)
150
°C
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, X1 pin only
Clock input
VDD/2 + 1 VDD/2
V
Input Low Voltage, VIL, X1 pin only
Clock input
VDD/2 VDD/2 - 1 V
Input High Voltage, VIH, all TI type inputs
VDD-0.5
V
Input Low Voltage, VIL, all TI type inputs
0.5
V
Input High Voltage, VIH, all I type inputs
2
V
Input Low Voltage, VIL, all I type inputs
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
60
mA
Short Circuit Current
Each output
Internal pull-up resistor
ACS1, BCS1, OE
AC CHARACTERISTICS (VDD = 5.0V unless noted)
±100
mA
200
kΩ
Input Frequency
10
12.5 or 25
27
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
50
60
%
Frequency error
All clocks
0
ppm
Absolute Jitter, short term
Variation from mean
150
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The ICS650-07C requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as
close to the ICS650-07 as possible. A series termination resistor of 33 Ω may be used for each clock output.
The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode
(do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to
ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the
following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal
with 16 pF load capacitance, two 20 pF caps should be used.
MDS 650-07C A
4
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
Share Link: 