HT9480(1998) データシートの表示（PDF） - Holtek Semiconductor

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HT9480
(Rev.:1998)

Pager Controller

Holtek Semiconductor 

HT9480

Reset

There are five ways in which a reset can occur:

• Power on reset (POR)

• RES reset during normal operation

• RES reset during HALT

• WDT time-out reset during normal operation

• WDT time-out reset during HALT

The WDT time-out during HALT is different

from other chip reset conditions, since it can

perform a “warm reset” that just resets the PC

and SP, leaving the other circuits to keep their

state. Some registers remain unchanged during

other reset conditions. Most registers are reset

to the “initial condition” when the reset condi-

tions are met. By examining the PD and TO

flags, the program can distinguish between dif-

ferent “chip resets”.

TO PD

RESET Conditions

0 0 Power on reset

u

u

RES reset during normal

operation

0 1 RES wake-up HALT

1

u

WDT time-out during normal

operation

1 1 WDT wake-up HALT

Note:“u” means “unchanged”

Reset configuration

If crystal mask option is selected, the µC clock

can be fed by X1, X2 decoder input clock (See

Application Circuit 2).

The functional units chip reset status is shown

in the following table.

PC

0000H

Interrupt

Disabled

Prescaler

Cleared

WDT

Cleared. After master

reset, WDT starts

counting.

Programmable

timer Counter

Off

Timer/event

Counter

Off

Programmable

Tone Generator

Off

Pager Decoder

Off

Input/output Ports input mode

SP

Points to the top of the

stack

Reset circuit

17

23th Feb ’98

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