HT9480(1998) データシートの表示（PDF） - Holtek Semiconductor

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HT9480
(Rev.:1998)

Pager Controller

Holtek Semiconductor 

HT9480

desired output of BZ is 2.73kHz, the frequency

source is 32.768kHz, the values of SPF10 and

SPF11 are both set to 0, and the value of the

programmable frequency divider is set to 5.

Input/Output ports

There are 7 input lines, and 10 input/output

lines in the HT9480, which are labeled as PA,

and PB; PC (PC0, PC1). These are mapped to

[12H], and [14H]; [16H] of the data memory,

respectively. Port A is an input port only while

Port B and Port C (PC0 and PC1) are bidirec-

tional I/O ports. For input operation, the ports

A, B, and C are non-latched, i.e., the inputs have

to be ready at the T2 rising edge of the instruc-

tion “MOV A, [m]” (m=12H, 14H, 16H). For

output operation, data is latched and then re-

mains unchanged until the output latch is re-

written.

The PB and PC (PC0, PC1) I/O lines have their

own control registers (PBC, PCC) to control the

input/output configuration. These control regis-

ters, tri-state (control register=1) or CMOS

(control register=0) with pull-high (option)

structures can be reconfigured dynamically

(i.e., on-the-fly) by software control. To function

as an input, the corresponding I/O latch and

related bit of the control register should be writ-

ten “1” to avoid external logical violation. These

control registers are mapped to location 15H,

and 17H (bit 0 and bit 1 of 17H).

After a chip reset, these input/output lines stay

at high levels or floating (by mask option). They

are defined as input types by writing “1” to the

control registers and as output types by writing

“0” to the control registers. Each bit of these

input/output latches can be set or cleared by

“SET [m].i” and “CLR [m].i” (m=14H only) in-

structions.

Some instructions first input data and then

follow the output operations. For example,

“SET [m].i”, “CLR [m].i”, “CPL [m]”, “CPLA [m]”

read the entire port states into the CPU, exe-

cute the defined operation (bit-operation), and

then write the results back to the latches or the

accumulator.

Each line of port A is capable of waking up the

device (when a falling edge occurs) and is deter-

mined by mask option. The highest four bits of

port C are not physically implemented. Reading

them gets a “0”, but writing them leads to no

operation.

Bit 7 of port A connects a battery fall interrupt

and a wake-up function. Bit 7 of port A wakes

up the µC each time a battery is changed. Bit 2

of port C is used for internal subsystem oscilla-

tor low-power function control (1: non-active; 0

: active). The value of bit 2 of port C is set as “1”

at an initial power on. Bit 3 of port C is used for

LCD power control (1: LCD turn-on; 0 : LCD

turn-off). The value of bit 3 of port C is also set

as “1” at the initial power on.

Input/output ports

21

23th Feb ’98

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