TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation
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TLIU04C1 Datasheet PDF : 100 Pages
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
Microprocessor Mode (continued)
Microprocessor Interface Register Architecture
The register bank architecture of TLIU04C1 consists of a register bank for the quad line interface unit. The register
bank consists of sixteen 8-bit registers comprising the alarm, control, and configuration registers for the quad line
interface unit.
Table 6 shows the register bank architecture.
Table 6. LIU Register Bank
Designation Address
Bit 7
0
0000
LOTC2
1
0001
LOTC4
2
0010
MLOTC2
3
0011
MLOTC4
Bit 6
Bit 5
Bit 4
Bit 3
Alarm Registers (Read Only)
TDM2
DLOS2
ALOS2
LOTC1
TDM4
DLOS4
ALOS4
LOTC3
Alarm Mask Registers (Read/Write)
MTDM2 MDLOS2 MALOS2 MLOTC1
MTDM4 MDLOS4 MALOS4 MLOTC3
Global Control Registers (Read/Write)
Bit 2
TDM1
TDM3
MTDM1
MTDM3
4
0100 HIGHZ4 (1) HIGHZ3 (1) HIGHZ2 (1) HIGHZ1 (1) ICTMODE (0) LOSSTD
5
0101
LOSSD
6
7
8
9
10
11
12
13
14—15
0110
0111
1000
1001
1010
1011
EQA1
EQA2
EQA3
EQA4
0
0
1100
CODE1
1101
0
1110—1111
ACM
ALM
DUAL
CODE
Channel Configuration Registers (Read/Write)
EQB1
EQC1
LOOPA1
LOOPB1
EQB2
EQC2
LOOPA2
LOOPB2
EQB3
EQC3
LOOPA3
LOOPB3
EQB4
EQC4
LOOPA4
LOOPB4
0
0
0
0
CODE3
0
CODE4
0
CODE2
JABW0
(0)
PHIZALM
(0)
PRLALM
(0)
0
0
0
0
RESERVED
JAT
XAIS1
XAIS2
XAIS3
XAIS4
0
0
PFLALM
(0)
0
Bit 1
Bit 0
DLOS1
DLOS3
ALOS1
ALOS3
MDLOS1
MDLOS3
MALOS1
MALOS3
SWRESET
(0)
GMASK (1)
JAR
CDR
MASK1
MASK2
MASK3
MASK4
0
0
RCVAIS
(0)
0
PWRDN1
PWRDN2
PWRDN3
PWRDN4
0
0
ALTIMER
(0)
0
Notes:
A numerical suffix appended to the bit name identifies the channel number.
Bits shown in parentheses indicate the state forced during a reset condition.
All registers must be configured by the user before the device can operate as required for the particular application.
Lucent Technologies Inc.
17
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