TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation

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TLIU04C1

Quad T1/E1 Line Interface

Agere -> LSI Corporation 

Advance Data Sheet, Rev. 2

April 1999

TLIU04C1 Quad T1/E1 Line Interface

Microprocessor Mode (continued)

Block Diagrams (continued)

The line interface block diagram is shown in Figure 3. For illustration purposes, only one of the four on-chip line

interfaces is shown. Pin names that apply to all four channels are followed by the designation [1—4].

ALOS

DLOS

RTIP[1—4]

RRING[1—4]

EQUALIZER

SLICERS

FLLOOP

(DURING LIU AIS)

CLOCK AND

DATA

RECOVERY

JITTER

ATTENUATOR

(RECEIVE PATH)

DECODER

FLLOOP

(NO LIU AIS)

TDM

LOTC

PULSE-

WIDTH

CONTROLLER

(CLOCK)

DLLOOP

RLOOP

TTIP[1—4]

TRING[1—4]

TRANSMIT

DRIVER

PULSE

EQUALIZER

(DATA)

JITTER

ATTENUATOR

(TRANSMIT PATH)

ENCODER

16x

CLOCK

MULTIPLIER

ALARM

INDICATION

SIGNAL (AIS)

LOSS

OF

TCLK

RND[1—4]

RPD[1—4]

RCLK[1—4]

TCLK[1—4]

TND[1—4]

TPD[1—4]

XCLK

CLKS

INTXCLK

DIVIDE BY 16

LOSS OF

XCLK

MONITOR

Figure 3. Block Diagram of the Quad Line Interface Unit (Single Channel)

LOXC

5-4556(F).er.3

Lucent Technologies Inc.

19

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