IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Memory Management System

The IDT79R3500 has an addressing range of 4GB. How-

ever, since most IDT79R3500 systems implement a physical

memory smaller than 4GBs, the IDT79R3500 provides for the

logical expansion of memory space by translating addresses

composed in a large virtual address space into available

physical memory address. Two TLB modes are supported.

When the TLB is used, the 4GB address space is divided into

2GBs which can be accessed by both the users and the

kernel, and 2GBs for the kernel only. Virtual addresses within

the kernel/user segment are translated to physical addresses

on a 4kB page basis. This mode is typical of UNIX and other

sophisticated operating systems. When the TLB is disabled,

mapping is locked as 2GBs as kernel/user, and 1.5GBs as

kernel only. This mode requires no TLB manipulation, pro-

vides large linear address space, and is typical for embedded

applications.

TLB (Translation Lookaside Buffer)

Virtual memory mapping is assisted by the Translation

Lookaside Buffer (TLB). The on-chip TLB provides very fast

virtual memory access and is well-matched to the require-

ments of multi-tasking operating systems. The fully-associa-

tive TLB contains 64 entries, each of which maps a 4kB page,

with controls for read/write access, cacheability, and process

identification. The TLB allows each user to access up to 2GBs

of virtual address space.

Figure 6 illustrates the format of each TLB entry. The

Translation operation involves matching the current Process

ID (PID) and upper 20 bits of the address against PID and VPN

(Virtual Page Number) fields in the TLB. When both match (or

the TLB entry is Global), the VPN is replaced with the PFN

(Physical Frame Number) to form the physical address.

TLB misses are handled in software, with the entry to be re-

placed determined by as imple RANDOM function. The rou-

tine to process a TLB miss in the UNIX environment requires

only 10-12 cycles, which compares favorably with many CPUs

which perform the operation in hardware.

TLB Disabled Operation

Many embedded systems do not like the complexity or

uncertainty associated with the on-chip TLB. However, many

systems still desire the ability to implement a kernel/user

mode. Therefore, to implement a hierachical task model, the

TLB must be used. The R3500 gives the system designer one

more option, allowing the TLB to be disabled and performing

a fixed mapping of virtual to physical addresses, while main-

taining separation of kernel and user resources.

The user may elect to disable the TLB through the reset

sectors. In this case, the mapping shown in Figure 8. is used,

and device power consumption is reduced. Note tha “cached“

segments means that there is no mechanism to exclude

addresses in these regions from the cache.

This mapping means that applications designed to run in

kseg0 and kseg1 (to avoid the TLB) can use the R3500,

disable the TLB to reduce power, and not have to change

software to take advantage of this new feature.

63

44 43

38 37

32 31

12 11 10 9 8 7

0

VPN

TLBPID

O

PFN

NDV G

O

ENTRYHI

VPN – Virtual Page Number

TLBPID – Process ID

PFN – Physical Frame Number

N – Non-cacheable flag

D – Dirty flag (Write protect)

V – Valid entry flag

G – Global flag (ignore PID)

O – Reserved

Figure 6. TLB Entry Format

ENTRYLO

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