SST45VF010 データシートの表示（PDF） - Silicon Storage Technology
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SST45VF010 Datasheet PDF : 16 Pages
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
Reset
Reset will terminate any operation, e.g., Read, Erase
and Program, in progress. It is activated by a high to low
transition on the RESET# pin. The device will remain in
reset condition as long as RESET# is low. Minimum reset
time is 10µs. See Figure 14 for reset timing diagram.
RESET# is internally pulled-up and could remain uncon-
nected during normal operation. After reset, the device is
in standby mode, a high to low transition on CE# is
required to start the next operation.
TABLE 1: PRODUCT IDENTIFICATION
Byte
Manufacturer’s ID
0000 H
Device ID
SST45VF512
0001 H
SST45VF010
0001 H
SST45VF020
0001 H
Data
BF H
41 H
45 H
43 H
514 PGM T1.4
An internal power-on reset circuit protects against acci-
dental data writes. Applying a logic level low to RESET#
during the power-on process then changing to a logic
level high when VDD has reached the correct voltage
level will provide additional protection against accidental
writes during power on.
Read SST ID/Read Device ID
The Read SST ID and Read Device ID operations read
the JEDEC assigned manufacturer identification and the
manufacturer assigned device identification codes.
These codes may be used to determine the actual device
resident in the system.
Write Protect
The WP# pin provides inadvertent write protection. The
WP# pin must be held high for any Erase or Program
operation. The WP# pin is “don’t care” for all other
operations. In typical use, the WP# pin is connected to
VSS with a standard pull-down resistor. WP# is then
driven high whenever an Erase or Program operation is
required. If the WP# pin is tied to VDD with a pull-up
resistor, then all operations may occur and the write
protection feature is disabled. The WP# pin has an
internal pull-up and could remain unconnected when not
used.
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Cell Array
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE# SCK SI SO WP# RESET#
© 2000 Silicon Storage Technology, Inc.
2
514ILL B1.0
S71178
514-1 10/00
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