MU9C8K64-50TDC データシートの表示（PDF） - Music Semiconductors

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MU9C8K64-50TDC

MU9C Routing Coprocessor (RCP) Family

Music Semiconductors 

MU9C Binary Routing Coprocessor (RCP) Family

Functional Description

When Hardware control is selected, control is through the

AC bus and DSC line. When Software control is selected,

control is through the Instruction register, which is loaded

from the DQ bus. Under software control the /AV line is

used to distinguish between data and an instruction on the

DQ bus. Therefore, in Software Control mode, random

access to the Memory array can take place only using

indirect addressing through the Address register.

The two Chip Select lines /CS1, /CS2 enable the device and

simplify access to a multi-chip system, if either Chip Select

line is LOW the device is selected. The MU9C RCP also

can be selected through the Device Select register when its

value is set to that of the Page address of the device, and the

enable bit in the Device Select register is set LOW. The /OE

input enables the output signal and is used to synchronize

devices in a multi-chip system, and to prevent race

conditions among devices during priority resolution.

The output signals comprise the Active address (AA bus),

and the Page address (PA bus). The PA:AA bus provides

the current Active address, which is either the Match

address, Next Free address, or the Random Access

address, concatenated with the Device Page address. The

source of Active address is dependent on the previous

control state, allowing access to associated data in the

external RAM at the same location as an access in the

MU9C RCP for all types of cycles.

The Output enable, /OE, controls the PA:AA bus: when it is

LOW after a Compare cycle, the highest-priority

responding device outputs its Page and Match addresses on

PA:AA bus. Only the highest-priority responding device is

enabled, all other lower-priority devices will have their

PA:AA bus in the high-impedance state, regardless of the

state of their respective /OE lines: when /OE is HIGH, the

PA:AA remain in the high-impedance state.

When a mismatch occurs in the system, the lowest-priority

device, as defined in the Configuration register, will drive

the PA:AA bus with all 1s. When any Read or Write cycle

occurs, the address of the accessed location is output on

the PA:AA bus. The address output on the PA:AA bus is

persistent, and is held latched until /E goes HIGH during

the next cycle that changes the Active address. The PA:AA

bus is free to change only while /E is HIGH. Once /E goes

LOW, the state of the PA:AA bus is latched.

After a Compare cycle, the /MF and /MM flags are free to

change after /E has gone HIGH. Once the Match Flag

daisy chain has resolved device prioritization, the /OE

lines can be asserted to enable the PA:AA bus from the

highest-priority matching device.

In a multi-chip system, when a device remains deselected

during a Compare cycle through /CS1 and /CS2 being

HIGH and there being no match between the Device

Select register and the Page Address register, that device

will clear any previous positive match results. In other

words, if it had previously been indicating a match from

an earlier Comparison cycle, it will now be set to indicate

a mismatch, even though it was not selected during the

most recent Compare cycle.

For pure software control of the MU9C RCP, instructions

can be loaded into the Instruction register, and results read

from the Status register. The Status register holds the

results of comparison: PA:AA bus, /MF, /FF, and /MM

plus two PA:AA Validation bits that indicate the type of

cycle that generated the PA:AA bus value.

Vertical cascading is supported through a daisy chain

architecture. There are two daisy chains, one each for the

Match flag and the Full flag; the Multiple Match flag is

connected between devices through an open-drain line.

The Match flag (/MF) from a higher-priority device is

connected to the Match input (/MI) of the next

lower-priority device to provide prioritization throughout

a multiple device system. The /MF output from the

lowest-priority device provides a system Match flag. If the

delay through the daisy chain is unacceptable, the /OE

input can be used by external priority-resolution circuitry

to enable the highest-priority responder in the system.

The match conditions on the Match and Multiple Match

flag lines are persistent indicating the results of the most

recent Compare cycle. The Match flags are free to change

after the rising edge of /E during a Compare cycle, at

which time the daisy chain starts to resolve device

prioritization. Once the daisy chain has settled, the /OE

lines can be pulled LOW to access the Highest-Priority

Match address on the PA:AA bus.

The Multiple Match open-drain output (/MM) provides

multiple match indication when there are two or more

matches in a single device, or a device has its /MI input

LOW and has a match; the /MM flags of all devices in the

system are wire-ORed. Multiple responders can be

accessed sequentially by resetting the Highest-Priority

Match latch with the control state Advance to Next

Matching Location.

The Full flag (/FF) is cascaded from one device to the Full

Flag input (/FI) of the next lower-priority device in the

system. The /FF output from the lowest-priority device

provides a system Full flag. The Full flag is free to change

after the rising edge of /E during a Write cycle. The daisy

chains are persistent and are not conditioned by the /OE

input.

The MU9C RCP supports JTAG boundary-scan testing

through the pins TCK, TMS, TDI, TDO, and /TRST,

according to the IEEE 1149 Standard: Test Access Port

and Boundary-scan Architecture.

6

Rev. 6

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