CC1020-1070DK-433 データシートの表示（PDF） - Unspecified
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CC1020-1070DK-433 Datasheet PDF : 92 Pages
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CC1021
4.7. Digital Inputs / Outputs
Parameter
Min Typ
Logic "0" input voltage
0
Logic "1" input voltage
Logic "0" output voltage
0.7*
VDD
0
Logic "1" output voltage
2.5
Logic "0" input current
NA
Logic "1" input current
NA
DIO setup time
20
DIO hold time
10
Serial interface (PCLK, PDI, PDO
and PSEL) timing specification
Pin drive, LNA_EN, PA_EN
0.90
0.87
0.81
0.69
0.93
0.92
0.89
0.79
Max
0.3*
VDD
VDD
Unit
V
V
Condition / Note
0.4
VDD
1
1
V Output current 2.0 mA,
3.0 V supply voltage
V Output current 2.0 mA,
3.0 V supply voltage
µA Input signal equals GND.
PSEL has an internal pull-up
resistor and during configuration
the current will be -350 µA.
µA Input signal equals VDD
ns TX mode, minimum time DIO
must be ready before the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
ns TX mode, minimum time DIO
must be held after the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
See Table 14 on page 24 for
more details
Source current
mA 0 V on LNA_EN, PA_EN pins
mA 0.5 V on LNA_EN, PA_EN pins
mA 1.0 V on LNA_EN, PA_EN pins
mA 1.5 V on LNA_EN, PA_EN pins
Sink current
mA 3.0 V on LNA_EN, PA_EN pins
mA 2.5 V on LNA_EN, PA_EN pins
mA 2.0 V on LNA_EN, PA_EN pins
mA 1.5 V on LNA_EN, PA_EN pins
See Figure 35 on page 61 for
more details.
Table 9. Digital inputs / outputs parameters
SWRS045
Page 14 of 91
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