CC1020-1070DK-433 データシートの表示（PDF） - Unspecified
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CC1020-1070DK-433 Datasheet PDF : 92 Pages
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CC1021
Pin no.
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
AGND
PCLK
PDI
PDO
DGND
DVDD
DGND
DCLK
DIO
LOCK
XOSC_Q1
XOSC_Q2
AVDD
AVDD
LNA_EN
PA_EN
AVDD
R_BIAS
AVDD
RF_IN
AVDD
RF_OUT
AVDD
AVDD
VC
AGND
AD_REF
AVDD
CHP_OUT
AVDD
DGND
DVDD
PSEL
Pin type
Ground (analog)
Digital input
Digital input
Digital output
Ground (digital)
Power (digital)
Ground (digital)
Digital output
Digital input/output
Digital output
Analog input
Analog output
Power (analog)
Power (analog)
Digital output
Digital output
Power (analog)
Analog output
Power (analog)
RF Input
Power (analog)
RF output
Power (analog)
Power (analog)
Analog input
Ground (analog)
Power (analog)
Power (analog)
Analog output
Power (analog)
Ground (digital)
Power (digital)
Digital input
Description
Exposed die attached pad. Must be soldered to a solid ground plane as
this is the ground connection for all analog modules. See page 63 for
more details.
Programming clock for SPI configuration interface
Programming data input for SPI configuration interface
Programming data output for SPI configuration interface
Ground connection (0 V) for digital modules and digital I/O
Power supply (3 V typical) for digital modules and digital I/O
Ground connection (0 V) for digital modules (substrate)
Clock for data in both receive and transmit mode.
Can be used as receive data output in asynchronous mode
Data input in transmit mode; data output in receive mode
Can also be used to start power-up sequencing in receive
PLL Lock indicator, active low. Output is asserted (low) when PLL is in
lock. The pin can also be used as a general digital output, or as receive
data output in synchronous NRZ/Manchester mode
Crystal oscillator or external clock input
Crystal oscillator
Power supply (3 V typical) for crystal oscillator
Power supply (3 V typical) for the IF VGA
General digital output. Can be used for controlling an external LNA if
higher sensitivity is needed.
General digital output. Can be used for controlling an external PA if
higher output power is needed.
Power supply (3 V typical) for global bias generator and IF anti-alias
filter
Connection for external precision bias resistor (82 kΩ, ± 1%)
Power supply (3 V typical) for LNA input stage
RF signal input from antenna (external AC-coupling)
Power supply (3 V typical) for LNA
RF signal output to antenna
Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA
stage
Power supply (3 V typical) for VCO
VCO control voltage input from external loop filter
Ground connection (0 V) for analog modules (guard)
3 V reference input for ADC
Power supply (3 V typical) for charge pump and phase detector
PLL charge pump output to external loop filter
Power supply (3 V typical) for ADC
Ground connection (0 V) for digital modules (guard)
Power supply connection (3 V typical) for digital modules
Programming chip select, active low, for configuration interface. Internal
pull-up resistor.
Table 11. Pin assignment overview
Note:
DCLK, DIO and LOCK are high-
impedance (3-state) in power down
(BIAS_PD = 1 in the MAIN register).
The exposed die attached pad must be
soldered to a solid ground plane as this is
the main ground connection for the chip.
SWRS045
Page 16 of 91
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