CC1020-1070DK-433 データシートの表示（PDF） - Unspecified

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CC1020-1070DK-433

Single Chip Low Power RF Transceiver

Unspecified 

CC1021

6. Circuit Description

RF_IN

RF_OUT

ADC

LNA

LNA 2

0

:2

90

0

:2

90

ADC

FREQ

SYNTH

Power

Control

Multiplexer

PA

BIAS

XOSC

PA_EN

LNA_EN

R_BIAS

XOSC_Q1 XOSC_Q2 VC CHP_OUT

Figure 2. CC1021 simplified block diagram

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

INTERFACE

TO µC

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

LOCK

DIO

DCLK

PDO

PDI

PCLK

PSEL

A simplified block diagram of CC1021 is

shown in Figure 2. Only signal pins are

shown.

CC1021 features a low-IF receiver. The

received RF signal is amplified by the low-

noise amplifier (LNA and LNA2) and

down-converted in quadrature (I and Q) to

the intermediate frequency (IF). At IF, the

I/Q signal is complex filtered and

amplified, and then digitized by the ADCs.

Automatic gain control, fine channel

filtering, demodulation and bit

synchronization is performed digitally.

CC1021 outputs the digital demodulated

data on the DIO pin. A synchronized data

clock is available at the DCLK pin. RSSI is

available in digital format and can be read

via the serial interface. The RSSI also

features a programmable carrier sense

indicator.

In transmit mode, the synthesized RF

frequency is fed directly to the power

amplifier (PA). The RF output is frequency

shift keyed (FSK) by the digital bit stream

that is fed to the DIO pin. Optionally, a

Gaussian filter can be used to obtain

Gaussian FSK (GFSK).

The frequency synthesizer includes a

completely on-chip LC VCO and a 90

degrees phase splitter for generating the

LO_I and LO_Q signals to the down-

conversion mixers in receive mode. The

VCO operates in the frequency range

1.608-1.880 GHz. The CHP_OUT pin is

the charge pump output and VC is the

control node of the on-chip VCO. The

external loop filter is placed between these

pins. A crystal is to be connected between

XOSC_Q1 and XOSC_Q2. A lock signal is

available from the PLL.

The 4-wire SPI serial interface is used for

configuration.

SWRS045

Page 17 of 91

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