PM25LV040-33QC データシートの表示（PDF） - PMC-Sierra, Inc

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PM25LV040-33QC

1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 33 MHz SPI Bus Interface

PMC-Sierra, Inc 

PMC

Pm25LV010/020/040

DEVICE OPERATION (CONTINUED)

FAST READ DATA OPERATION

The Pm25LV010/020/040 also feature a Fast Read

(FAST_READ) instruction. This FAST_READ instruction

is used to read memory data in 33 MHz clock rate where

the FAST_READ instruction proceeding.

The devices are first selected by driving CE# low (VIL).

The FAST_READ instruction code followed by three bytes

address (A23 - A0) and a dummy byte (8 clocks) is

trasmitted via the SI line, each bit being latched-in dur-

ing the rising edge of SCK. Then the first data byte

addressed is shifted out on SO line, each bit being shifted

out at a maximum frequency fCT, during the falling edge

of SCK.

The first byte addressed can be at any location. The

address is automatically incremented to the next higher

address after each byte of data is shifted out. When the

highest address is reached, the address counter will roll

over to the 000000h address allowing the entire memory

to be read with a single FAST_READ instruction. The

FAST_READ instruction is terminated by driving CE#

high (VIH).

Figure 12. Fast Read Data Sequence

CE#

0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31

SCK

3-BYTE ADDRESS

SI

INSTRUCTION = 0000 1011b 23 22 21 ... 3 2 1 0

SO

CE#

SCK

SI

SO

HIGH IMPEDANCE

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

DUMMY BYTE

7 654321 0

HIGH IMPEDANCE

DATA OUT 1

7 6 54 3 21 0

DATA OUT 2

7 6 54 3 21 0

Programmable Microelectronics Corp.

17

Issue Date: July, 2005, Rev: 1.2

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