K9LBG08U0D データシートの表示（PDF） - Samsung
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K9LBG08U0D Datasheet PDF : 74 Pages
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K9HCG08U1D K9PDG08U5D
K9LBG08U0D K9MDG08U5D
Preliminary
FLASH MEMORY
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB doesn’t need to be page 0.
Page 127
Page 31
Page 2
Page 1
Page 0
(128)
:
(32)
:
(3)
(2)
(1)
Page 127
Page 31
Page 2
Page 1
Page 0
(128)
:
(1)
:
(3)
(32)
(2)
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
Data (128)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (128)
Interleaving operation
DDP device is composed of two chips sharing CE pin. DDP device provides interleaving operation between two chips
This interleaving operation improves the system throughput almost twice compared to non-interleaving operation.
At first, the host issues a operation command to one of the LSB chips, say (chip #1). Due to DDP device goes into busy state. During
this time, MSB chip (chip #2) is in ready state. So it can execute the operation command issued by the host.
After the execution of operation by LSB chip (chip #1), it can execute another operation regardless of MSB chip (chip #2). Before that
the host needs to check the status of LSB chip (chip #1) by issuing F1h command. Only when the status of LSB chip (chip #1)
becomes ready status, host can issue another operation command. If LSB chip (chip #1) is in busy state, the host has to wait for LSB
chip (chip #1) to get into ready state.
Similarly, MSB chip (chip #2) can execute another operation after the completion of the previous operation. The host can monitor the
status of MSB chip (chip #2) by issuing F2h command. When MSB chip (chip #2) shows ready state, host can issue another opera-
tion command to MSB chip (chip #2).
This interleaving algorithm improves the system throughput almost twice. The host can issue page operation command to each chip
individually. This reduces the time lag for the completion of operation.
NOTES : During interleave operations, 70h command is prohibited.
Table . F1h/F2h Read Status Register Definition
I/O No.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Page Program
Chip Pass/Fail
Plane0 Pass/Fail
Plane1 Pass/Fail
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
Block Erase
Chip Pass/Fail
Plane0 Pass/Fail
Plane1 Pass/Fail
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
Read
Not use
Not use
Not use
Not Use
Not Use
Not Use
Ready/Busy
Write Protect
Definition
Pass : "0"
Fail : "1"
Pass : "0"
Fail : "1"
Pass : "0"
Fail : "1"
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Ready : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
Samsung Confidential
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