11525-801 データシートの表示（PDF） - AMI Semiconductor
部品番号
コンポーネント説明
メーカー
11525-801 Datasheet PDF : 26 Pages
| |||
X T
)6)6
&ORFN *HQHUDWRU ,& IRU ,QWHO 3HQWLXP ,, %; 3& 6\VWHPV
April 1999
Table 9: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
100MHz
66.67MHz
UNITS
MIN. TYP. MAX. MIN. TYP. MAX.
Overall
Spread Spectrum Modulation
Frequency *
fm
SS_EN# low
31.5
31.5 kHz
Spread Spectrum Modulation
Profile *
SS_EN# low
Lexmark
Lexmark
Spread Spectrum Modulation
Index *
δm
SS_EN# low
-0.5
-0.5
%
CPU to CPU @ 1.25V, CL=20pF
66 175
50 175
Clock Skew *
tskw
APIC to APIC @ 1.25V, CL=20pF
32 175
24 175
ps
PCI to PCI @ 1.5V, CL=30pF
48 500
48 500
Clock Offset *
tpd
CPU @ 1.25V, CL = 20pF to
PCI @ 1.5V, CL = 30pF
1.5 1.73 4.0 1.5 1.88 4.0
ns
Tristate Enable Delay *
tDZL, tDZH SEL_0:1 and SEL_100/66# = 0 1.0
8.0 1.0
8.0
ns
Tristate Disable Delay *
tDZL, tDZH SEL_0:1 and SEL_100/66# = 0 1.0
8.0 1.0
8.0
ns
Clock Stabilization (on power-up) *
tSTB
via PWR_DWN#
1.5 3.0
1.6 3.0
ms
CPU_0:3 Clock Outputs (2.5V Type 1 Clock Buffer)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Enable Delay *
Disable Delay *
Ratio of high pulse width, as measured
from rising edge to next falling edge at
45
1.25V, to one clock period
55
45
55
%
tj(LT)
On rising edges 500µs apart at 1.25V
relative to an ideal clock, CL=20pF, all
PLLs active
295
296
ps
tj(∆P)
From rising edge to next rising edge at
1.25V, CL=20pF, all PLLs active
145 250
182 250
ps
tr min
tr max
Measured @ 0.4V – 2.0V; CL = 10pF
Measured @ 0.4V – 2.0V; CL = 20pF
0.4 0.8
0.4 0.8
ns
1.1 1.6
1.1 1.6
tf min
tf max
Measured @ 2.0V – 0.4V; CL = 10pF
Measured @ 2.0V – 0.4V; CL = 20pF
0.4 1.0
0.4 1.0
ns
1.1 1.6
1.1 1.6
tDLH
via CPU_STOP#
7
38
11
42
ns
tDHL
via CPU_STOP#
2
33
3
34
ns
APIC_0:1 Clock Output (2.5V Type 2 Clock Buffer)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Ratio of high pulse width, as measured
from rising edge to next falling edge at
45
1.25V, to one clock period
55
45
55
%
On rising edges 500µs apart at 1.25V
tj(LT)
relative to an ideal clock, CL=20pF, all
50
PLLs active
35
ps
tj(∆P)
From rising edge to next rising edge at
1.25V, CL=20pF, all PLLs active
215
237
ps
tr min
tr max
Measured @ 0.4V – 2.0V; CL = 10pF
Measured @ 0.4V – 2.0V; CL = 20pF
0.4 1.1
0.4 1.1
ns
1.3 1.6
1.3 1.6
tf min
tf max
Measured @ 2.0V – 0.4V; CL = 10pF
Measured @ 2.0V – 0.4V; CL = 20pF
0.4 0.6
0.4 0.6
ns
0.8 1.6
0.8 1.6
4.5.99
,62
11
Share Link: 