GL603USB データシートの表示（PDF） - Genesys Logic
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GL603USB Datasheet PDF : 41 Pages
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GL603USB/GL603USB-A/GL603USB-B
endpoint 0 data is received (both SETUP and OUT transaction) and should be cleared by firmware
after data is read from FIFO.
0: Endpoint 0 FIFO is available for data receiving
FFRST0: Reset endpoint 0 FIFO read/write pointer
Write “1” to this bit will reset endpoint 0 FIFO read/write pointer. Data in endpoint 0 FIFO remain
unchanged. Before data are written into endpoint 0 FIFO, FFRST0 should be written first.
TXSEQ0: Endpoint 0 transmitting sequence bit
1: Transmitting data use DATA 1 as PID
0: Transmitting data use DATA 0 as PID
TXOE0: Endpoint 0 FIFO data ready bit
1: Endpoint 0 FIFO data are ready to be transmitted. Data will be transmitted when a valid IN
token is received. This bit is automatically cleared by hardware after the transaction complete
(ACK is received).
0: Endpoint 0 FIFO data are not ready to be transmitted and respond with a NAK to a valid IN
transaction.
Value on POR: “- 0 0 0 0 0 0 0”
Note 1: “W/O” means write-only bit. 0 will be returned when reading this bit
FFDAT0 (Address 17h, Endpoint 0 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Endpoint 0 FIFO data port
Endpoint 0 FIFO is a 8 bytes FIFO. Firmware can read/write this port 8 times to get/put the FIFO
data.
Value on POR: “x x x x x x x x”
FFDAT1 (Address 18h, Endpoint 1 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Endpoint 1 FIFO port
Endpoint 1 FIFO is 8 bytes FIFO. Firmware can read this port 8 times to get the FIFO data.
Value on POR: “x x x x x x x x”
EP0RXST (Address 19h, Endpoint 0 receiving status register)
R/O
R/O
R/O
R/O
RXST3
RXST2
RXST1
RXST0
RXST[3:0]: If EP0RX is set, then there’s a complete transaction. RXST[3:0] indicate the packet received.
Bit Value
Packet received
1001
SETUP token with DATA0 packet
0101
OUT token with DATA0 packet
0110
OUT token with DATA1 packet
Value on POR: “- - - - x x x x”
4.3 MCU FUNCTION REGISTERS
Address
00h
01h
02h
03h
04h
Name
INDR
TIMER
PCL
STATUS
INDAR
Function
Addressing this location will use the content of INDAR to address data
memory (not a physical address)
Timer register
Program Counter’s low byte
Status register
Indirect address register
16
09/22/00
Revision 1.4
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