HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
12.5.1.2 READ Access Timing (Burst Mode)
BCLK
RA
nRCS
nROE
N
tSU(A)
tSU(CE0)
N+1
N+2
N+3
tHO(A)
tHO(CE1)
tSU(CE1)
tSU(D)
tHO(D)
RD
Symbol
Parameter
Min Max Unit
tSU(A)
Address to nRCS falling-edge setup time
13
tHO(A)
nROE rising-edge to Address hold time
-15
tSU(CE0)
nRCS falling-edge to nROE falling-edge setup time
13
tHO(CE0)
nROE rising-edge to nRCS rising-edge setup time
-13
tHO(CE1) nROE or nRWE rising-edge to nRCS falling-edge hold time 25
ns
tSU(CE1) nROE or nRWE rising-edge to nRCS falling-edge setup time 50
tSU(D)
Data setup time before latch
5
tHO(D)
Data hold time after latch
0
Timing values for read access in burst mode data transfer
Memory Configuration Register Setting = 0xE00
11 10 9
8
7
1
1100
6
5
4
3
0000
2
1
0
0
00
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Version 1.1
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