HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

2.2.2 Multiple Function Pins

2.2.2.1 PORT A

Data Input/Output

Primary

(nTEST

nPLLENABLE)

~AEN* &

~AMULSEL**

GPIO Enable

MultiFunction BOTH Enable

| (nTEST

| Enable

(nTEST

|

& nPLLENABLE ) & (nTEST

| nPLLENABLE ) &

AEN &

nPLLENABLE ) & AEN &

~AMULSEL

~AEN &

AMULSEL

AMULSEL

I

O

I

O

I

O

I

KSCANO0 PORTA0 PORTA0

PORTA0 PORTA0

KSCANO1 PORTA1 PORTA1

PORTA1 PORTA1

KSCANO2 PORTA2 PORTA2

PORTA2 PORTA2

KSCANO3 PORTA3 PORTA3

PORTA3

KSCANO4 PORTA4 PORTA4

PORTA4

KSCANO5 PORTA5 PORTA5 USIN2

PORTA5

KSCANO6 PORTA6 PORTA6

USOUT2 PORTA6

KSCANO7 PORTA7 PORTA7

IRDOUT PORTA7

KSCANI0

PORTA8 PORTA8

PORTA8 PORTA8

KSCANI1

PORTA9 PORTA9

PORTA9 PORTA9

KSCANI2

PORTA10 PORTA10

PORTA10 PORTA10

KSCANI3

PORTA11 PORTA11

PORTA11

KSCANI4

PORTA12 PORTA12

PORTA12

KSCANI5

PORTA13 PORTA13 USIN3

PORTA13

KSCANI6

PORTA14 PORTA14

USOUT3 PORTA14

KSCANI7

PORTA15 PORTA15 IRDIN

PORTA15

* AEN : GPIO PORT A Enable Register (0x8002.301C).

** AMULSEL : GPIO PORT A Multi-Function Select Register (0x8002.30A4).

O

PORTA0

PORTA1

PORTA2

PORTA3

PORTA4

PORTA5

PORTA6

PORTA7

PORTA8

PORTA9

PORTA10

PORTA11

PORTA12

PORTA13

PORTA14

PORTA15

Analog Test

(~nTEST & ~nPLLENABLE)

I

TPLL3FREQSEL[0]

TPLL3FREQSEL[1]

TPLL3FREQSEL[2]

TPLL3FREQSEL[3]

TPLL3FREQSEL[4]

TPLL3FREQSEL[5]

TPLL3PWDN

TAIOSTOP

TACH[0]

TACH[1]

TACH[2]

TACH[3]

TACH[4]

O

TPLL3CLKOut

TPLL3CLKQOut

TPLL3LOCKOut

2.2.2.2 PORT B

Data Input/Output

Primary

nTEST

~nPLLENABLE

~BEN*

GPIO Enable

& nTEST

& ~nPLLENABLE

BEN

Normal Bypass

& nTEST

&

& nPLLENABLE

I

O

I

O

I

O

nURING

PORTB0 PORTB0 nURING

nUDTR

PORTB1 PORTB1

nUDTR

nUCTS

PORTB2 PORTB2 nUCTS

nURTS

PORTB3 PORTB3

nURTS

nUDSR

PORTB4 PORTB4 nUDSR

nUDCD

PORTB5 PORTB5 nUDCD

PORTB6

PORTB6 PORTB6 PORTB6 TBFCLK

PORTB7

PORTB7 PORTB7 PORTB7 TBQFCLK

PORTB8

PORTB8 PORTB8 PORTB8 TBBCLK

PORTB9

PORTB9 PORTB9 PORTB9

PORTB10 PORTB10 PORTB10 PORTB10 TBLCLK

PORTB11 PORTB11 PORTB11 PORTB11 TBCCLK

* BEN : GPIO PORT B Enable Register (0x8002.303C).

Normal TEST

~nTEST

&

nPLLENABLE &

~BEN

I

O

TBLCLK

TBCCLK

TBFCLK

TBQFCLK

TBBCLK

TREQB

TREQA

TACK

UART TEST

~nTEST

&

nPLLENABLE &

BEN

I

O

nURING

nUDTR

nUCTS

nURTS

nUDSR

nUDCD

TREQB

TREQA

TACK

Analog Test

~nTEST

&

~nPLLENABLE

I

O

TACLK

TAD[9]

TAD[8]

TAD[7]

TREQB

TREQA

TACK

© 2004 MagnaChip Semiconductor Ltd. All Ri2g0hts Reserved.

- 20 -

Version 1.1

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