DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

HMS30C7202N データシートの表示(PDF) - MagnaChip Semiconductor

部品番号
コンポーネント説明
メーカー
HMS30C7202N
Magnachip
MagnaChip Semiconductor Magnachip
HMS30C7202N Datasheet PDF : 179 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
HMS30C7202N
2.2.2.3 PORT C
Data Input/Output
Primary
GPIO Enable
Analog Test
(nTEST | nPLLENABLE) & ~CEN* (nTEST | nPLLENABLE) ~nTEST
&
& CEN
~nPLLENABLE
I
O
I
TIMEROUT
PORTC0
PORTC1
PORTC1
PORTC1
PORTC2
PORTC2
PORTC2
PSDAT
PSDAT
PORTC3
PSCLK
PSCLK
PORTC4
PWM0
PORTC5
PWM1
PORTC6
nDMAREQ
PORTC7
nDMAACK
PORTC8
nRCS2 /
[nRCS2dma]
PORTC9
nRCS3
PORTC10
* CEN : GPIO PORT C Enable Register (0x8002.305C).
O
PORTC0
PORTC1
PORTC2
PORTC3
PORTC4
PORTC5
PORTC6
PORTC7
PORTC8
PORTC9
PORTC10
I
TDIOSTOP
TDLEFT
TDD[2]
TDD[1]
O
TAD[2]
TAD[4]
TAD[3]
TAD[1]
TAD[0]
TDD[0]
2.2.2.4 PORT D
Data Input/Output
Primary
GPIO Enable
(nTEST | nPLLENABLE ) (nTEST | nPLLENABLE )
& ~DEN*
& DEN
I
O
I
O
LD8
PORTD0
LD9
PORTD1
LD10
PORTD2
LD11
PORTD3
LD12
PORTD4
LD13
PORTD5
LD14
PORTD6
LD15
PORTD7
LBLEN
PORTD8
z DEN : GPIO PORT D Enable Register (0x8002.307C).
PORTD0
PORTD1
PORTD2
PORTD3
PORTD4
PORTD5
PORTD6
PORTD7
PORTD8
Analog Test
~nTEST & ~nPLLENABLE
I
O
TPLL1PWDN
TPLL1FREQSEL[0]
TPLL1FREQSEL[1]
TPLL1FREQSEL[2]
TPLL1FREQSEL[3]
TPLL1FREQSEL[4]
TPLL1FREQSEL[5]
TPLL1PCLKIn
© 2004 MagnaChip Semiconductor Ltd. All Ri2g1hts Reserved.
- 21 -
Version 1.1

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]