HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
4 MEMORY MAP
There are five main memory map divisions, outlined in Table 4-1 Top-level address map
Base Address (Byte) Base Address (Hex)
0 Mbyte
0x0000.0000
64 Mbytes
0x0400.0000
128 Mbytes
0x0800.0000
192 Mbytes
0x0C00.0000
256 Mbytes
0x1000.0000
512 Mbytes
0x2000.0000
1024 Mbytes
0x4000.0000
1056 Mbytes
0x4200.0000
1088 Mbytes
0x4400.0000
1120 Mbytes
0x4600.0000
1152 Mbytes
0x4800.0000
2048 Mbytes
0x8000.0000
Table 4-1 Top-level address map
Size
32Mbytes
32Mbytes
32Mbytes
32Mbytes
256Mbytes
512Mbytes
32Mbytes
32Mbytes
896Mbytes
336Kbytes
Description
ROM chip select 0
ROM chip select 1
ROM chip select 2
ROM chip select 3
Reserved
Reserved
SDRAM chip select 0
SDRAM chip select 1
SDRAM mode register chip 0
SDRAM mode register chip 1
Reserved
Peripherals
The ROM has an address space of 256Mbytes that is split equally between four external ROM chip select.
Actual address range for each chip select is 32Mbytes with 25 external address signals.
There is a maximum of 64Mbytes of SDRAM space. Reading from the address space(over 0x4400.0000)
above the SDRAM address space(0x4000.0000~0x43ff.ffff) sets the mode registers in the SDRAM (To set the
SDRAM mode register, read operation from the ranges of SDRAM mode register is needed. For more
information, refer 6.3. ).
The peripheral address space is subdivided into three main areas: those on the ASB, the fast APB and the
slow APB. The base address for the peripherals is given in Table 3-2: Peripherals base addresses.
Function
ASB Peripherals
Fast APB Peripherals
Slow APB Peripherals
Base Address (Hex)
0x7F00.0000
0x7F00.0800
0x8000.0000
0x8000.1000
0x8000.2000
0x8000.3000
0x8000.4000
0x8000.5000
0x8001.0000
0x8001.1000
0x8001.2000
0x8001.3000
0x8001.4000
0x8001.5000
0x8001.6000
0x8001.7000
0x8002.0000
0x8002.1000
0x8002.2000
0x8002.3000
0x8002.4000
0x8002.5000
0x8002.6000
0x8002.8000
0x8002.9000
0x8002.A000
0x8002.B000
Name
IntSRAM Base
Reserved
SDRAMC Base
PMU Base
Reserved
BUSC Base
DMAC Base
Reserved
LCD
Reserved
USB Base
Sound Base
Reserved
MMC Base
SMC Base
Reserved
U0 Base
U1 Base
KBD Base
GPIO Base
INTC Base
Timer Base
Reserved
RTC Base
ADC Base
Reserved
WDT Base
Description
Internal SRAM
~0x7FFF.FFFF
SDRAM Controller
PMU/PLL
Bus controller
DMAC
~0x8000.FFFF
LCD
USB
SOUND
MMC/ SPI
SMC
~0x8001.FFFF
UART 0
UART 1 (support SIR)
KBD
GPIO
INTC
TIMER
~0x8002.7FFF
RTC
ADC
WDT
© 2004 MagnaChip Semiconductor Ltd. All Ri2g5hts Reserved.
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Version 1.1
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