HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
SLOW
The CPU is switched into FastBus mode, and hence runs at the BCLK rate (half the FCLK rate). This is the
default mode after exiting SLEEP Mode.
IDLE
In this mode, the PMU becomes the bus master until there is either a fast or normal interrupt for the CPU, or
the peripheral DMA controller requests master-ship of the bus.
This will cause the clocks in the CPU to stop when it attempts an ASB access. This mode can be initiated by
writing the PMU_IDLE value to the PMU Mode Register (in RUN or SLOW mode), or by a WakeUp signal
while the CPU is in SLEEP or DEEP SLEEP mode.
SLEEP
In this mode, the SDRAM is put into self-refresh mode, and internal clocks are gated off. This mode can only
be entered from IDLE mode (the PMU bus master must have mastership of the ASB before this mode can be
entered). The PMU must be bus master to ensure that the system is stopped in a safe state, and is not half
way through a SDRAM write (for example). Both the Video and Communication clocks should be disabled
before entering this state.
Usually this state would only be entered briefly, on the way to entering DEEP SLEEP mode.
DEEP SLEEP
In DEEP SLEEP mode, the 3.6864MHz oscillator and the PLL are disabled. This is the lowest power state
available. Only the 32 kHz oscillator runs, driving the real time clock and the PMU. Clocked circuitry in the
PMU runs at 4kHz (i.e. the RTC clock divided by 8). Everything else is powered down, and SDRAM is in self
refresh mode. This is the normal system "off" mode.
SLEEP and DEEP SLEEP modes are exited either by a user wake-up event (generally pressing the "On" key),
or by an RTC wake-up alarm, or by a modem ring indicate event. These interrupt sources go directly to the
PMU.
5.2.3 Wake-up Debounce and Interrupt
The Wake-up events are debounced as follows:
Each of the event signals which are liable to noise (nRESET, RTC, nPMWAKEUP, and Modem Ring Indicator,
Power Adapter Condition) is re-timed to a 250 Hz clock derived from the low power (4 kHz) clock. After filtering
to a quarter of 250 Hz, each event has an associated `sticky' register bit. nPMWAKEUP is an external input,
which may be typically connected to an "ON" key.
A `sticky' bit is a register bit that is set by the incoming event, but is only reset by the CPU. Thus should a PLL
drop out of lock momentarily (for example) the CPU will be informed of the event, even if the PLL has regained
lock by the time the CPU can read its associated register bit.
The nPMWAKEUP, Modem, Real Time Clock, HotSync(GPIOB[10]) and Power Adapter condition inputs are
combined to form the PMU Interrupt. Each of these four interrupt sources can wake up from deep-
sleep mode individually and all wake-up operation can not mask able. But when wake-up occur,
user can mask interrupt signal to inform interrupt controller.
To make use of the nPMWAKEUP Interrupt, (for example) controlling software will need to complete the
following tasks:
z Enable the nPMWAKEUP interrupt bit, by writing 1 to bit[11] of the Reset / Status register (PMUSTAT
register).
z Once an interrupt has occurred, read the RESET / Status register to identify the source(s) of interrupt. In the
case of a nPMWAKEUP event, the register will return 0x10.
z Clear the appropriate `sticky' bit by writing a 1 to the appropriate location (in the nPMWAKEUP case, this
will be 0x10.).
But Even though the nPMWAKEUP interrupt mask bit is masked, by writing 0 to bit[11] of the Reset Status
register, chip shall wake-up with nPMWAKEUP signal.
PORTB[10] (HotSync) Wake-up Sequence
The HotSync interrupt is OR gated with nPMWAKEUP to support additional wake up sources.
HotSync input signal can be used as a wake up source; they are enabled using the Interrupt MASK Register.
After wake up, s/w should program the PORTB Interrupt Mask Register and/or the PMU ResetStatus Register.
© 2004 MagnaChip Semiconductor Ltd. All Ri2g9hts Reserved.
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