HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

frequency of 58.9824Mhz.

z The CPU may write 0xE120 to the Clock Control register, which enables CCLK and VCLK, and retains the new FCLK

frequency.

Bit

Meaning

Bit 0 set:

Power On Reset event has occurred

Bit 1 set:

PLL1 has been `unlocked'

Bit 2 set:

PLL2 has been `unlocked'

Bit 3 set:

PLL3 has been `unlocked'

Table 5-2 PMU Bit Settings for a cold Reset Event within PMUSTAT Register

5.4.2 Software Generated Warm Reset

Figure 5-3 PMU Software Generated Warm Reset

The CPU writes `1' to the WarmReset bit of PMUSTAT register. The PMU drives nRESET low. The internal

chip reset, BnRES is driven low. The PMU detects that the bi-directional nRESET pin is low. nRESET is

filtered by a de-bounce circuit. Note that this means that nRESET will remain low for a minimum of 16ms.

BnRES becomes active once the de-bounced nRESET goes high once more, which disables PLL1 and PLL2.

The CPU may read the PMUSTAT register, which will return 0x106:

Bit

Meaning

Bit 1 set:

PLL1 has been `unlocked'

Bit 2 set:

PLL2 has been `unlocked'

Bit 8 set:

A RESET event has occurred.

Table 5-3 PMU Bit Settings for a Software Generated Warm Reset within PMUSTAT Register

5.4.3 An Externally generated Warm Reset

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