MSM514212 データシートの表示（PDF） - Oki Electric Industry

部品番号

コンポーネント説明

メーカー

MSM514212

5,048-Word x 8-Bit Line Memory

Oki Electric Industry 

¡ Semiconductor

MSM514212

OPERATION MODE

Write Cycle

When WE input is enabled (at the "L" level), the write cycle is executed by synchronizing it with

the WCK clock input. Read and write data is processed by the same clock in the write cycle to

carry out the video processing. Data is input after a delay of oneline (5048 bits) is input at the

rising edge of the clock in the write cycle.

In addition, when the length of the delay is controlled by WE, the value of the delay bits is from

40 to 5048. The WR operation must be performed now to write the last data to memory cell.

Read Cycle

When RE input is enabled (at the "L" level), the read cycle is executed by synchronizing it with

the RCK clock input. Data is output at tAC (or tACR). In addition, when the length of the delay

is controlled by RE, the value of the delay bits is from 40 to 5048.

Write Reset Cycle

Read Reset Cycle

When the power supply is on, the address values of the read and write address pointers are at

random. Thus, each pointer must be initialized by the RR signal and the WR signal beforehand.

Data can be input (to address 0) with the first cycle after this reset operation.

Power-up and Initialization

On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has

stabilized to a value within the range of recommended operating conditions. After this 100 ms

stabilization interval, the following initialization sequence must be performed.

Because the read and write address counters are not valid after power-up, a minimum of 18

dummy write operations (WCK cycles) and read operations (RCK cycles) must be performed,

followed by a WR operation and an RR operation, to properly initialize the write and the read

address pointer. Dummy write cycles/WR and dummy read cycles/RR may occur simultaneously.

If these dummy read and write operations start while VCC and/or the substrate voltage has not

stabilized, it is necessary to perform an RR operation plus a minimum of 18 RCK cycles plus

another RR operation, and a WR operation plus a minimum of 18 WCK cycles plus another WR

operation to properly initialize read and write address pointers.

8/15

Share Link: