MT47H128M8HW-3M データシートの表示（PDF） - Micron Technology
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MT47H128M8HW-3M Datasheet PDF : 133 Pages
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Figure 5: 64 Meg x 16 Functional Block Diagram
1Gb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
ODT
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
Control
logic
Mode
registers
16
A0–A12,
BA0–BA2
16
Address
register
Refresh
counter
13
13
3
10
13
Row-
address
MUX
Bank 7
Bank 7
Bank 6
Bank 6
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
row-
address
latch
8,192
Memory array
(8,192 x 256 x 64)
and
decoder
Sense amplifier
16,384
64
2
Bank
control
logic
I/O gating
DM mask logic
256
(x64)
COL0, COL1
CK, CK#
64 Read
latch
16
16
16
16
16
MUX DATA
DLL
DRVRS
DQS
4
generator UDQS, UDQS#
Input LDQS, LDQS#
registers
2
2
WRITE
FIFO
64
and
drivers
2
82
Mask 2
16
2
22
2
RCVRS
16
Column- 8
address
counter/
2
latch
Column
decoder
CK, CK#
CK out
CK in
64 16
Data 16
16
COL0, COL1
16 16
16
16
4
ODT
sw1
control
sw2 sw3
VDDQ
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQ0–DQ15
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
UDQS, UDQS#
LDQS, LDQS#
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
UDM, LDM
VSSQ
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
13
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