8600V データシートの表示（PDF） - Lattice Semiconductor

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8600V

3.3V In-System Programmable SuperBIG™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 8600V

Figure 3. ispLSI 8000V Macrocell Overview

Single PT

PTSA

PTSA Bypass

PT Clock

Global Clock Enable

Global Clock 0

Global Clock 1

Global Clock 2

PT Reset

GRST

PT Preset

Reset pin

GRST

Preset/Reset Input has Global Polarity Control

*Not available for Macrocells 9 and 10.

From PT80

DQ

Clk En

R/L

RP

Bus Input From Tristate

Bus Track*

Feedback to AND Array

To Big Fast Megablock

or Global Interconnect

To Specific

Global Tristate Bus*

From Macrocell

9 or 10

To All Macrocells and I/O Cells

: Function Selector (E2 Cell Controlled)

6

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