CY7C1486V33(2004) データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C1486V33
(Rev.:2004)

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan Order-165FBGA

Boundary Scan Order-209BGA

PRELIMINARY

CY7C1480V33

CY7C1482V33

CY7C1486V33

Bit Size (x36)

3

1

32

73

-

Bit Size (x18)

3

1

32

54

-

Bit Size (x72)

3

1

32

-

112

Identification Codes

Instruction

EXTEST

IDCODE

SAMPLE Z

RESERVED

SAMPLE/PRELOAD

RESERVED

RESERVED

BYPASS

Code

000

001

010

011

100

101

110

111

Description

Captures the I/O ring contents.

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

Do Not Use: This instruction is reserved for future use.

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Boundary Scan Order (x36)

Bit #

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

165-Ball ID

C1

D1

E1

D2

E2

F1

G1

F2

G2

J1

K1

L1

J2

M1

N1

K2

L2

M2

R1

R2

R3

P2

R4

P6

R6

Boundary Scan Order (x36) (continued)

Bit #

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

165-Ball ID

N6

P11

R8

P3

P4

P8

P9

P10

R9

R10

R11

N11

M11

L11

M10

L10

K11

J11

K10

J10

H11

G11

F11

E11

D10

Document #: 38-05283 Rev. *C

Page 16 of 30

Share Link: